Patent
Application-specific testing methods for programmable logic devices
Robert W. Wells,Zhi-Min Ling,Robert D. Patrie,Vincent L. Tong,Jae Cho,Shahin Toutounchi,Clay S. Johnson,Shelly G. Davis +7 more
- 26 Jul 2002
61
TL;DR: In this paper, the authors present methods for utilizing programmable logic devices that contain at least one localized defect, such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect.
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Abstract: Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.
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Citations
•Book
FPGA Architecture: Survey and Challenges
Ian Kuon,Russell Tessier,Jonathan Rose +2 more
- 18 Apr 2008
TL;DR: This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures.
Patent
Programmable system on a chip
Gregory Bakker,Khaled A. El-Ayat,Theodore Speers,Limin Zhu,Brian Schubert,Rabindranath Balasubramanian,Kurt Kolkind,Thomas F. Barraza,Venkatesh Narayanan,John L. McCollum,William C. Plants +10 more
- 10 May 2004
TL;DR: A programmable interconnect architecture includes programmable elements and interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, analog sub-system, the analog input/output circuit block, and the digital input and output circuit block can be programmably coupled to one another.
124
Patent
Error detection on programmable logic resources
Ninh D. Ngo,Andy L. Lee,Kerry Veenstra +2 more
- 10 Oct 2002
TL;DR: In this article, an output indicating whether an error is detected is generated depending on the relationship between the checksum and the expected value, or on the value of the checkum.
111
Patent
Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits
Stephen M. Trimberger
- 01 Oct 2004
TL;DR: In this article, a user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream and stored along with associated test bitstreams in a memory device, e.g., a programmable read-only memory (PROM).
48
Patent
Integrated circuit including programmable logic and external-device chip-enable override control
Rabindranath Balasubramanian,Kurt Kolkind,Gregory Bakker +2 more
- 31 Oct 2007
TL;DR: In this paper, an integrated circuit device includes a programmable logic block, a monitoring input, a condition sensing circuit coupled to the monitoring input and configured to generate a condition-sensed signal at an output in response to sensing a condition at the monitor input.
35
References
•Book
Application-Specific Integrated Circuits
Michael John Sebastian Smith
- 01 Jan 1997
TL;DR: This book provides the first comprehensive introduction to Application Specific Integrated Circuits (ASICs) with a focus on semi-custom technology.
524
Patent
FPGA repeatable interconnect structure with hierarchical interconnect lines
Steven P. Young,Kamal Chaudhary,Trevor J. Bauer +2 more
- 26 Feb 1997
TL;DR: In this paper, a combination of single-length lines connecting to adjacent tiles and intermediate-length line connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles, and tiles some distance away.
249
Patent
Method for manufacturing test simulation in electronic circuit design
Mauro V. Tegethoff
- 07 Feb 1995
TL;DR: The manufacturing and test simulator (MTSIM) as discussed by the authors simulates manufacturing test and repair aspects of boards and multichip modules (MCMs) from design concept through manufacturing release to aid the designer in selecting appropriate trade-offs in the design for manufacturability and testability.
191
Patent
Configurable cellular array.
Thomas A. Kean
- 17 Mar 1990
TL;DR: In this article, a configurable cellular array is provided having a 2-dimensional array of cells in which each cell in the array has at least one input and output connection at least 1 bit wide to its neighbours.
190
Dynamic fault tolerance in FPGAs via partial reconfiguration
John M. Emmert,Charles E. Stroud,B. Skaggs,Miron Abramovici +3 more
- 17 Apr 2000
TL;DR: On-line, multi-level fault tolerant (FT) technique for system functions and applications mapped to partially and dynamically reconfigurable FPGAs based on the roving self testing areas (STARs) fault detection/location strategy.
150
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