Application Experiences with a Real-Time Java Processor

TL;DR: This book complements the thesis and provides insight into the implementation of JOP and the accompanying JVM, and gives you an idea how to build an embedded real-time system based on JOP.

TL;DR: This paper shows cache simulation results for the split-cache organization, proposes the modularization of the data cache analysis for the different data areas, and evaluates the implementation costs in a prototype chip-multiprocessor system.

TL;DR: This paper proposes interactive WCET analysis as a new method to provide near-instantaneous WCET feedback to the developer during software programming and shows that tree-based analysis scales better with respect to program size and gives similar WCET values.

TL;DR: A static analysis for this cache is designed and implemented, and integrated into a worst-case execution time analysis tool, and a small, highly associative cache is proposed for the heap area.

TL;DR: An overview of the Time-Triggered Architecture is given, the architectural principles are discussed, the sensor/actuator interfaces in the TTA are described, the implementation of fault-tolerance is informed and the provision of fully specified interfaces between subsystems is described.

TL;DR: It is demonstrated that a hardware implementation of the Java virtual machine results in a small design for resource-constrained devices.

TL;DR: This small, flexible microprocessor core provides performance five to 20 times better than other means of Java execution and the microarchitecture trade-offs made for picoJava-I are illustrated.

TL;DR: This thesis presents a Java processor designed for time-pre dictable execution of real-time tasks and introduces a processor architectur in which simpler and more accurate WCET analysis is more important than average case p erformance.