Patent
Apparatus and method for memory with bit swapping on the fly and testing
R. Paul Dixon,David R. Resnick,Gerald A. Schwoerer,Kelly J. Marquardt,Alan M. Grossmeier,Michael L. Steinberger,Van L. Snyder,Roger A. Bethard,Michael F. Higgins +8 more
- 19 May 2004
80
TL;DR: In this paper, a memory controller and method that provides a read-refresh (also called "distributed refresh") mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-resh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the readrefresh operation, rather than being an independent operation.
read more
Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Patent
Disabling outbound drivers for a last memory buffer on a memory channel
Pete D. Vogt,Dennis W. Brzezinski,Warren R. Morrow +2 more
- 07 Sep 2012
TL;DR: A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bits and the memory device as mentioned in this paper.
6
Patent
Memory subsystem with positional read data latency
Kevin C. Gower,Kevin W. Kark,Mark W. Kellogg,Warren E. Maule +3 more
- 11 Feb 2009
TL;DR: In this article, a memory subsystem with positional read data latency that includes one or more memory modules, a memory controller and one or multiple memory busses is provided, where the memory modules and the memory controller are interconnected via the memory buses.
6
Patent
Semiconductor package of stacked chips having an improved data bus structure, semiconductor memory module and semiconductor memory system having the same
Chung Hoe Ju
- 18 Jun 2010
TL;DR: In this paper, a semiconductor package of stacked chips having an improved data bus structure is provided to efficiently transmit data by supplying an optimum bus structure according to a bank, a bank group, and a rank.
5
Patent
Resolving cache lookup of large pages with variable granularity
Ahmed Gheith,Eric Van Hensbergen,James Xenidis +2 more
- 04 Nov 2013
TL;DR: In this paper, a method, system, and computer program product for resolving cache lookup of large pages with variable granularity are provided in the illustrative embodiments, where a number of unused bits in an available number of bits is identified.
5
Patent
Method for selecting memory busses according to physical memory organization information associated with virtual address translation tables
Robert B. Tremaine
- 06 Jan 2009
TL;DR: In this paper, a memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory, which includes a plurality of memory devices organized into one or more physical groups accessible via associated busses.
5
References
Patent
Solid state memory system including plural memory chips and a serialized bus
Robert D. Norman,Karl M. J. Lofgren,Jeffrey Donald Stai,Anil Gupta,Sanjay Mehrotra +4 more
- 26 Jul 1991
TL;DR: In this paper, a memory system includes an array of solid-state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines.
289
Patent
Multiprocessor node controller circuit and method
Martin M. Deneroff,Givargis G. Kaldani,Yuval Koren,David Edward Mccracken,Swaminathan Venkataraman +4 more
- 29 Sep 2000
TL;DR: In this article, the first node controller is fabricated onto a single integrated-circuit chip and the memory is packaged on plugable memory/directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset devoted to holding directory data.
212
Patent
Serial architecture for memory module control
Darrell L. Cox
- 12 Oct 1993
TL;DR: An expandable memory system as discussed by the authors includes a central memory controller and one or more plug-in memory modules, each memory module having an on-board memory module controller coupled in a serial network architecture which forms a memory command link.
178
Patent
Error-correcting system
Genzo Dipl Ing Nagano,Masao Takahashi +1 more
- 29 Aug 1980
TL;DR: In this paper, an error-correcting system between a main memory and a central processing unit is described, which includes a relief bit memory, an ECC or Error Correction Code logic circuit, a switching circuit and a correction controlling circuit.
111
Patent
Method and apparatus for support of multiple memory devices in a single memory socket architecture
Stephen J. Doyle
- 28 Sep 1998
TL;DR: In this article, an apparatus and method for supporting multiple types and configurations of random access memory devices in a single dual in line memory module (DIMM) socket architecture is provided.
105
Related Papers (5)
Andreas Jakobs,Hermann Ruckerbauer,Maksim Kuzmenka +2 more
- 08 Jul 2004
Peter Vogt
- 20 May 2004
John B. Halbert,Randy M. Bonella +1 more
- 02 Oct 2002