Journal Article10.1016/J.MSSP.2016.10.051
Analytical modeling of subthreshold characteristics of ion-implanted symmetric double gate junctionless field effect transistors
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TL;DR: In this article, a 2D analytical model for the sub-threshold current and sub-reshold swing of ion-implanted double-gate junctionless field effect transistors (DG-JLFETs) with a vertical Gaussian-like doping profile is presented.
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About: This article is published in Materials Science in Semiconductor Processing. The article was published on 01 Feb 2017. The article focuses on the topics: Subthreshold slope & Subthreshold conduction.
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Citations
Impact of Gaussian Doping Profile and Negative Capacitance Effect on Double-Gate Junctionless Transistors (DGJLTs)
Hema Mehta,Harsupreet Kaur +1 more
TL;DR: In this paper, the impact of vertical Gaussian doping (GD) profile and ferroelectric (FE) negative capacitance phenomenon on the performance of nanoscale double-gate junctionless (JL) transistor was investigated.
33
Impact of uniform and non-uniform doping variations for ultrathin body junctionless FinFETs
TL;DR: In this article, the impact of Fin width (Fw), Fin height (Fh), Channel length (Lg) and Gate Oxide (tox) on drain current, ION/IOFF ratio, subthreshold swing, Drain Induced Barrier Lowering (DIBL) of Si-based Bulk Junctionless FinFETs is investigated.
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Dual-Channel Junctionless FETs for Improved Analog/RF Performance
TL;DR: In this article, a dual-channel single gate junctionless FET (DCJLT) is investigated to improve the analog/RF performance, where the gate of proposed structure is placed in a vertical trench and two channels are taken on both sides of the gate.
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A new trench double gate junctionless FET: A device for switching and analog/RF applications
TL;DR: In this article, a trench double-gate junctionless FET (TDG-JLFET) is proposed for switching and analog/RF applications, where the gates are placed vertically in separate trenches for better control over the channel electrostatics.
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Ultrathin body nanowire hetero-dielectric stacked asymmetric halo doped junctionless accumulation mode MOSFET for enhanced electrical characteristics and negative bias stability
TL;DR: In this paper, the authors presented a 2D analytical model of ultrathin hetero dielectric, asymmetric halo doped graded channel (HDGC) nanowire junctionless accumulation mode (JAM) MOSFETs.
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References
Nanowire transistors without junctions
Jean-Pierre Colinge,Chi-Woo Lee,Aryan Afzalian,Aryan Afzalian,Nima Dehdashti Akhavan,Ran Yan,Isabelle Ferain,Pedram Razavi,B. O'Neill,Alan Blake,Mary White,Anne-Marie Kelleher,Brendan McCarthy,Richard Murphy +13 more
TL;DR: A new type of transistor in which there are no junctions and no doping concentration gradients is proposed and demonstrated, which has near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
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Junctionless multigate field-effect transistor
Chi-Woo Lee,Aryan Afzalian,Nima Dehdashti Akhavan,Ran Yan,Isabelle Ferain,Jean-Pierre Colinge +5 more
TL;DR: In this article, the authors describe a metaloxide-semiconductor MOS transistor concept in which there are no junctions and the channel doping is equal in concentration and type to the source and drain extension doping.
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Performance estimation of junctionless multigate transistors
Chi-Woo Lee,Isabelle Ferain,Aryan Afzalian,Ran Yan,Nima Delidashti Akhavan,Pedrarn Razavi,Jean-Pierre Colinge +6 more
TL;DR: In this paper, the authors describe the simulation of the electrical characteristics of a new transistor concept called the junctionless multigate field effect transistor (MuGFET), which has no junctions, a simpler fabrication process, less variability and better electrical properties than classical inversionmode devices with PN junctions at the source and drain.
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Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors
TL;DR: In this article, a bulk current model for long-channel double-gate junctionless (DGJL) transistors was formulated using a depletion approximation, and an analytical expression was derived from the Poisson equation to find channel potential.
A Full-Range Drain Current Model for Double-Gate Junctionless Transistors
TL;DR: In this article, a drain current model for long-channel double-gate junctionless transistors was derived by extending the concept of parabolic potential approximation for the subthreshold and the linear regions.