Journal Article10.1109/JSSC.2019.2936765
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators
Juyeop Kim,Younghyun Lim,Heein Yoon,Yongsun Lee,Hangi Park,Yoonseo Cho,Taeho Seong,Jaehyouk Choi +7 more
46
TL;DR: A cascaded architecture of a frequency synthesizer to generate ultra-low-jitter output signals in a millimeter-wave frequency band from 28 to 31 GHz is presented and the optimally spaced voltage comparators (OSVCs) are presented as a voltage quantizer.
read more
Abstract: This article presents a cascaded architecture of a frequency synthesizer to generate ultra-low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The mmW-band injection-locked frequency multiplier (ILFM) placed at the second stage has a wide bandwidth so that the performance of the jitter of this frequency synthesizer is determined by the GHz-band, digital subsampling phase-locked loop (SSPLL) at the first stage. To suppress the quantization noise of the digital SSPLL while using a small amount of power, the optimally spaced voltage comparators (OSVCs) are presented as a voltage quantizer. This article was designed and fabricated using 65-nm CMOS technology. In measurements, this prototype frequency synthesizer generated output signals in the range of 28–31 GHz, with an rms jitter of less than 80 fs and an integrated phase noise (IPN) of less than −40 dBc. The active silicon area was 0.32 mm2, and the total power consumption was 41.8 mW.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
Mario Mercandelli,Alessio Santiccioli,Angelo Parisi,Luca Bertulessi,Dmytro Cherniak,Andrea L. Lacaita,Carlo Samori,Salvatore Levantino +7 more
TL;DR: In this paper, a fractional-N sampling type-I phase-locked loop (PLL) is presented, where a digital phase error correction (DPEC) technique, operating in the background, is introduced, which provides robust low-jitter performance.
31
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push–Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM
TL;DR: In this article , an integer-N-type-II sub-sampling phase-locked loop (SS-PLL) was proposed to suppress the spur-induced binary frequency shift keying modulation (BFSK) effect and shorten the settling time.
28
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator
TL;DR: This work presents a low-jitter, low-reference-spur ring voltage-controlled oscillator (ring VCO)-based injection-locked clock multiplier (ILCM) based on the proposed triple-point frequency/phase/slope calibrator (TP-FPSC), which allows the ILCM to achieve a very low-RMS jitter.
20
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-<i>N</i> Digital PLL Using a DTC’s Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM
01 Sep 2022
TL;DR: In this paper , a low-jitter and low-spur, fractional ring-oscillator-based digital phase-locked loop (RO-DPLL) is presented.
14
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier
Yongwoo Jo,Juyeop Kim,Yuhwan Shin,Hangil Park,Chanwoong Hwang,Younghyun Lim,Jae-Hak Choi +6 more
TL;DR: A wideband LO generator for 5G FR1 bands is presented, utilizing a single LC-VCO-based subsampling PLL and a ring-VCO-based fractional-resolution frequency multiplier, achieving ultra-low jitter and phase noise with a power consumption of 17.9 mW.
13
References
Least squares quantization in PCM
TL;DR: In this article, the authors derived necessary conditions for any finite number of quanta and associated quantization intervals of an optimum finite quantization scheme to achieve minimum average quantization noise power.
Least Squares Quantization in PCM
S. P. Lloyd
- 01 Jan 1982
TL;DR: The corresponding result for any finite number of quanta is derived; that is, necessary conditions are found that the quanta and associated quantization intervals of an optimum finite quantization scheme must satisfy.
9.6K
A filtering technique to lower LC oscillator phase noise
Emad Hegazi,Henrik Sjöland,Asad A. Abidi +2 more
- 05 Feb 2001
TL;DR: Based on a physical understanding of phase-noise mechanisms, a passive LC filter was found to lower the phasenoise factor in a differential oscillator to its fundamental minimum in this paper.
A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time
Daniel Schinkel,E. Mensink,E. Kiumperink,E. van Tuijl,Bram Nauta +4 more
- 18 Jun 2007
TL;DR: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage, which enables fast operation over a wide common-mode and supply voltage range as discussed by the authors.
A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$
TL;DR: This paper presents a 2.2-GHz low jitter sub-sampling based PLL that uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock that guarantees correct frequency locking without degenerating jitter performance when in lock.