An optimal algorithm for sizing sequential circuits for industrial library based designs
Sanghamitra Roy,Yu Hen Hu,Charlie Chung-Ping Chen,Shih-Pin Hung,Tse-Yu Chiang,Jiuan-Guei Tseng +5 more
- 21 Jan 2008
- pp 148-151
TL;DR: This method is the first exact gate sizing algorithm that can handle cyclic sequential circuits and can yield an average of 12.6% improvement in the optimal clock period by combining clock skew optimization with gate sizing.
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Abstract: In this paper, we propose an optimal gate sizing and clock skew optimization algorithm for globally sizing synchronous sequential circuits. The number of constraints and variables in our formulation is linear with respect to the number of circuit components and hence our algorithm can efficiently find the optimal solution for industrial scale designs. To the best of our knowledge our method is the first exact gate sizing algorithm that can handle cyclic sequential circuits. Experimental results on industrial cell libraries demonstrate that our algorithm can yield an average of 12.6% improvement in the optimal clock period by combining clock skew optimization with gate sizing. For identical clock period, our algorithm can achieve an average of 11.3% area savings over a popular commercial synthesis tool.
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Citations
Library-Based Cell-Size Selection Using Extended Logical Effort
TL;DR: A new delay-bounded dynamic programming-based algorithm was developed that achieves, for the first time, active area versus delay results close to the continuous results, which is the first continuous-cell sizing technique exhibiting optimality based upon a table-lookup delay model.
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Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach
Ankur Sharma,David Chinnery,Chris Chu +2 more
- 04 Apr 2019
TL;DR: This work modifications a LR discrete gate sizing formulation with table lookup non-convex delay models, which are more accurate for modern process technologies, and uses a projection heuristic that is much faster than solving the minimum cost network flow problem.
8
Simultaneous clock and data gate sizing algorithm with common global objective
Gregory Shklover,Ben Emanuel +1 more
- 25 Mar 2012
TL;DR: An algorithm that performs gate sizing circuit optimization for VLSI designs by extending traditional gate sizing by Lagrangian Relaxation method with clock-related formulations and using Dynamic Programming to solve those optimally.
8
Implications of Modern Semiconductor Technologies on Gate Sizing
John Hyung Lee
- 01 Jan 2012
TL;DR: This work provides methods for gate sizing with statistical delay, and compute bounds to show that full statistical power optimization is not essential, and provides a method to perform incremental discrete gate sizing to account for both anticipated and unanticipated changes in the manufacturing process parameters.
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Lagrangian relaxation-based multi-threaded discrete gate sizer
Ankur Sharma
- 01 Jan 2018
TL;DR: FAST LAGRANGIAN RELAXATION BASed GATE SIZING USING MULTITHREADING BASed Gate Sizing Contests and Thesis Outline .
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