Proceedings Article10.1109/ISICIR.2016.7829734
An on-chip integrated III–V / CMOS 125MSps 6-bit SAR ADC
Sunny Sharma,Siau Ben Chiah,Xing Zhou,Chirn Chye Boon +3 more
- 01 Dec 2016
- pp 1-4
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TL;DR: A fully integrated on-chip III–V HEMT and CMOS hybrid technology, implementing a 6b 125MSps successive approximation register (SAR) ADC, results in reduction of parasitic elements, enhance the settling speed and superior dynamic performance.
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Abstract: This paper presents a fully integrated on-chip III–V HEMT and CMOS hybrid technology, implementing a 6b 125MSps successive approximation register (SAR) ADC. On-chip integration is achieved by using a hybrid PDK that permits direct integration of Au-free III–V devices into a foundry-proven CMOS process. The prototype utilizes an on-chip integrated InGaAs sampling switch and remaining circuits in CMOS. A “more than Moore” design and fabrication methodology has been adopted to overcome CMOS performance limitation. On-chip InGaAs switch integration results in reduction of parasitic elements, enhance the settling speed and superior dynamic performance. In this work the ADC consumes 1.99mW from a 1.8V supply achieving 33.7dB SNDR at nyquist and occupies 0.0225mm2.
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