An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs

Question

1. What are the contributions in "An integer-linear-programming-based routing algorithm for flip-chip designs" ?

2. What is the first stage of detailed routing?

3. How can the authors accomplish detailed routing in the first phase?

4. Why is the ILP-based algorithm able to find high quality solutions in reasonable CPU times?

Accepted Answer

The flip-chip package provides a high chip-density solution to the demand for more input–output pads of very large scale integration designs.. In this paper, the authors present the first routing algorithm in the literature for the preassignment flip-chip routing problem with a predefined netlist among pads and wire-width and signal-skew considerations.. Without loss of the solution optimality, their reduction techniques can further prune the ILP variables ( constraints ) by 85. 5 % ( 98. 0 % ) on average over a recent reduction technique.

Accepted Answer

In the second stage of detailed routing, the authors use passing-point assignment, net-ordering determination, and X-based gridless routing to determine the detailed routes.

Accepted Answer

By using the result of global routing, the passing-point assignment, and the segment compaction, their algorithm can accomplish detailed routing in the first phase.

Accepted Answer

Due to the significant reductions and the optimality guarantee, their ILP-based algorithm is able to find very high quality solutions in reasonable CPU times.

Accepted Answer

The objective in detailed routing is to accomplish the routing and minimize the number of wire bends after passing-point assignment and net ordering determination.

Accepted Answer

Since their nonmonotonic routing network contains monotonic routing solutions, the authors can still get the monotonic routing result by using the ILP.

Accepted Answer

After accomplishing detailed routing in the first phase, the authors perform bend minimization net by net and reduce the total wirelength at the same time.

Accepted Answer

Problem 1: The single-layer preassignment routing problem in the FC design is to connect a set P of wire-bonding pads and a set B of bump pads according to a predefined netlist with wire width and signal skew constraints, so that no wire crosses each other, no signal skew constraint is violated, and the total wirelength is minimized under the 100% routability guarantee.

Accepted Answer

Since the network-flow approach cannot guarantee the correct connections between two designated nodes, it cannot handle the preassignment routing problem.

Accepted Answer

For other cases, the constraint-graphbased pruning and the ILP node merging can further reduce the numbers of nodes and edges in the routing network; this is because when the authors increase the number of edges in the constraint graph, some ILP nodes can be further pruned.

Accepted Answer

For [1], [2], and [12] on the planar routing, since modules with pins can be placed anywhere in a chip, it is harder and has been shown to be NP-complete, and, thus, most likely, there exists no efficient optimal algorithm for the planar routing.

Accepted Answer

Note that the congestion avoidance gives the reason why the authors can handle variable wire widths and guarantee 100% routability after global routing.

Accepted Answer

The authors also must avoid the congestion overflow of an interval between two pads; therefore, the authors have constraint (3) for the edges passing through the same interval.

Accepted Answer

If ei,j crosses ep,q , C(ei,j , ep,q) = 1; otherwise, C(ei,j , ep,q) = 0.6) Pi(ei,j): function that denotes the connection of ei,j and wire-bonding pad pi ∈ P .

Accepted Answer

In this paper, the authors present the first algorithm for the preassignment RDL routing problem, considering signal skews, variablewire widths, U-turn routes, and total wirelength minimization.

Accepted Answer

If ei,j is in interval u, Hu(ei,j) = 1; otherwise, Hu(ei,j) = 0. 12) hu: constant that denotes the routing resource of interval u ∈ U . 13) si,p: constant that denotes the maximum allowance of the signal skew between net i and net p.

Accepted Answer

Fang et al. [6], [8] have addressed the free-assignment routing problem and presented a network-flow algorithm to assign wire-bonding pads to bump pads.

Accepted Answer

Theorem 1: Given set P of wire-bonding pads, set B of bump pads, and set N of nets, the number of edges of the routing network G = (V,E) can be reduced from O(|N |aa) to O(|N |a3), where a = √ |B|, with the constraint-graphbased pruning and the ILP node merging.

Accepted Answer

For the worst-case scenario of the ILP node merging, no edge and node can be reduced by the merging when the constraint graph induces only one net order.

An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs

Chat with Paper

AI Agents for this Paper

Most frequently asked questions

1. What are the contributions in "An integer-linear-programming-based routing algorithm for flip-chip designs" ?

2. What is the first stage of detailed routing?

3. How can the authors accomplish detailed routing in the first phase?

4. Why is the ILP-based algorithm able to find high quality solutions in reasonable CPU times?

5. What is the objective of detailed routing?

6. How can the authors get the monotonic routing result?

7. How do the authors reduce the total wirelength?

8. What is the routability guarantee for the wire-bonding pads?

9. Why does the network-flow approach not handle the preassignment routing problem?

10. What is the way to reduce the number of nodes in the routing network?

11. What is the way to solve the planar routing problem?

12. What is the reason why the RDL can be routable?

13. What is the constraint for the edges passing through the same interval?

14. what is the function that denotes the connection of ei,j and the wire?

15. What is the first algorithm for the preassignment RDL routing problem?

16. What is the maximum allowance of the signal skew between u and u?

17. What is the way to solve the preassignment routing problem?

18. What is the simplest way to reduce the number of edges of the routing network?

19. What is the way to reduce the edge and node?

Figures

Citations

Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs

Consumer Electronics Product Manufacturing Time Reduction and Optimization using AI-based PCB and VLSI Circuit Designing

Obstacle-Aware Group-Based Length-Matching Routing for Pre-Assignment Area-I/O Flip-Chip Designs

A study of row-based area-array I/O design planning in concurrent chip-package design flow

ILP-based inter-die routing for 3D ICs

References

Computers and Intractability: A Guide to the Theory of NP-Completeness

A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design

An integer linear programming based routing algorithm for flip-chip design

A routing algorithm for flip-chip design

Single-layer global routing

Related Papers (5)

A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design

Flip-chip routing with unified area-I/O pad assignments for package-board co-design

Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews

An integer linear programming based routing algorithm for flip-chip design

Area-I/O flip-chip routing for chip-package co-design