Proceedings Article10.1109/GLSV.1999.757426
An incremental floorplanner
J. Crenshaw,Majid Sarrafzadeh,Prithviraj Banerjee,P. Prabhakaran +3 more
- 04 Mar 1999
- pp 248-251
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TL;DR: A novel floorplanner, with a new wiring metric, which can be updated quickly in small increments, which provides tools with a way to influence the floorplan as they make changes without large running time penalty.
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Abstract: One of the foremost problems in physical design for deep-submicron circuits is the need for estimates that depend on future decisions. Estimation of area, timing, and coupling are required. We propose a novel floorplanner, with a new wiring metric, which can be updated quickly in small increments. This provides tools with a way to influence the floorplan as they make changes without large running time penalty. We provide experimental results that show the incremental approach to be generally 5 times faster than full floorplanning while maintaining good estimates.
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Citations
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Incremental physical design
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- 12 Mar 2001
TL;DR: In this paper, the authors formulate and survey fundamental problems in incremental physical design and provide preliminary solutions to a subset of these problems, and discuss the potential of such problems in the context of CAD tools.
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Incremental physical design
Jason Cong,Majid Sarrafzadeh +1 more
- 01 May 2000
TL;DR: The author states that "V" A i3J / -" 3T Q #4 H 3 ?
72
Quality of EDA CAD tools: definitions, metrics and directions
Amir H. Farrahi,D.J. Hathaway,M. Wang,Majid Sarrafzadeh +3 more
- 20 Mar 2000
TL;DR: The need for rethinking quality models used in EDA tools to allow early and reliable planning, estimation, analysis, and optimization, and methodologies and directions for the next generation design automation tools are discussed.
58
Incremental CAD
Olivier Coudert,Jason Cong,Sharad Malik,Majid Sarrafzadeh +3 more
- 05 Nov 2000
TL;DR: Fundamental problems in incremental logic synthesis and physical design are outlined and preliminary solutions to a subset of these problems are outlined.
50
A novel thermal optimization flow using incremental floorplanning for 3D ICs
Xin Li,Yuchun Ma,Xianlong Hong +2 more
- 19 Jan 2009
TL;DR: Experimental results show that migrating computation, growing unit and moving hotspot can reduce max on-chip temperature by 7%, 13% and 15% respectively on MCNC/GSRC benchmarks, and experimental results also show that the thermal optimization flow can achieve better area and total wirelength improvement than individual operations do.
34
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Giovanni De Micheli
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TL;DR: This book covers techniques for synthesis and optimization of digital circuits at the architectural and logic levels, i.e., the generation of performance-and-or area-optimal circuits representations from models in hardware description languages.
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Daniel D. Gajski,Nikil Dutt,Allen C.H. Wu,Steve Y-L Lin +3 more
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Architectural power analysis: The dual bit type method
Paul E. Landman,Jan M. Rabaey +1 more
TL;DR: A novel strategy for generating accurate black-box models of datapath power consumption at the architecture level by recognizing that power consumption in digital circuits is affected by activity, as well as physical capacitance.
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Path-based scheduling for synthesis
TL;DR: A novel path-based scheduling algorithm that yields solutions with the minimum number of control steps, taking into account arbitrary constraints that limit the amount of operations in each control step, is presented.
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3D scheduling: high-level synthesis with floorplanning
Jen-Pin Weng,Alice C. Parker +1 more
- 01 Jun 1991
TL;DR: A new approach to the problem of scheduling while simultaneously considering floorplanning is presented and an algorithm to reduce interconnection cost by introducing redundant operators is proposed.
111
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