An improved hierarchical classification algorithm for structural analysis of integrated circuits
Markus Olbrich,A. Rein,Erich Barke +2 more
- 13 Mar 2001
- pp 807
TL;DR: A new and efficient combination of signal tracing and block recognition techniques for circuit analysis that is applicable to various circuit types and works on several abstraction levels is proposed.
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Abstract: A new and efficient combination of signal tracing and block recognition techniques for circuit analysis is proposed. It utilizes the benefits of both approaches to solve problems such as signal flow or gate recognition. The analysis process is easily controlled by a user definable rule set where ports, nets and block are attributed with types. After structural investigation a hierarchical netlist is produced providing block information as subcircuits. As an important feature, the algorithm allows the handling of optional ports as well. Thus, this flexible approach is applicable to various circuit types and works on several abstraction levels.
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Citations
Patent
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TL;DR: In this paper, a method for generating a layout for an analog circuit design is provided, which includes tracing a signal flow through a circuit netlist, and partitioning the circuit net list into a digital portion and an analog portion.
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Marko Milosevic
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References
SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm
Miles Ohlrich,Carl Ebeling,Eka Ginting,Lisa Sather +3 more
- 01 Jul 1993
TL;DR: In this article, the problem of finding subcircuits in a larger circuit is solved using an extension of the graph partitioning algorithm used by Gemini for graph isomorphism, and experimental results show that the typical running time for large CMOS circuits is approximately linear in the total number of devices within the sub-circuits being matched.
146
Extracting RTL models from transistor netlists
K. J. Singh,P. A. Subrahmanyam +1 more
- 01 Dec 1995
TL;DR: This paper addresses the problem of deriving a register-transfer level (RTL) model from a transistor-level circuit by converting the circuit into a relation that describes the evolution of the signals in the circuit with respect to the simulator clock.