Book Chapter10.1007/978-3-540-45234-8_29
An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm
G. P. Saggese,Antonino Mazzeo,Nicola Mazzocca,Antonio G. M. Strollo +3 more
- 01 Sep 2003
- pp 292-302
143
TL;DR: The design and the FPGA implementation of a fully key agile AES encryption core with 128-bit keys, and the proposed implementations of AES achieve better performance as compared to other blocks in the literature and commercial IP core on the same device.
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Abstract: In October 2000 the National Institute of Standards and Technology chose Rijndael algorithm as the new Advanced Encryption Standard (AES). AES finds wide deployment in a huge variety of products making efficient implementations a significant priority. In this paper we address the design and the FPGA implementation of a fully key agile AES encryption core with 128-bit keys. We discuss the effectiveness of several design techniques, such as accurate floorplanning, the unrolling, tiling and pipelining transformations (also in the case of feedback modes of operation) to explore the design space. Using these techniques, four architectures with different level of parallelism, trading off area for performance, are described and their implementations on a Virtex-E FPGA part are presented. The proposed implementations of AES achieve better performance as compared to other blocks in the literature and commercial IP core on the same device.
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Citations
A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA
TL;DR: The PPR architecture fills the gap between unrolling and rolling architectures and is suitable for small and medium-sized FPGAs, and can be implemented on the minimum-sized Stratix FPGA while the unrolling implementation cannot.
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AES Encryption Algorithm Hardware Implementation Architecture: Resource and Execution Time Optimization
Samir El Adib,Naoufal Raissouni +1 more
TL;DR: An architecture to implement Advanced Encryption Standard (AES) Rijndael algorithm in reconfigurable hardware in FPGA that can be used in a wide range of embedded applications is presented and compared with other reference implementations.
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IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration
TL;DR: This work presents the experience in implementing two different cryptographic algorithms in an FPGA: IDEA and AES, done by means of mixing Handel-C and VHDL and using partial and dynamic reconfiguration to reach very high performance.
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Studies on high-speed hardware implementation of cryptographic algorithms
Kimmo Järvinen
- 01 Jan 2008
TL;DR: This dissertation aims to provide a history of signal processing technology and its applications in the field of telecommunications, as well as some of the techniques used in modern signal processing.
ECRYPT Yearly Report on Algorithms and Keysizes (2007-2008)
Christian Rechberger,Vincent Rijmen +1 more
- 01 Jan 2008
TL;DR: The report provides a list of recommended cryptographic algorithms and recommended keysizes and other parameter settings to reach specified security objectives and the fact that a specific algorithm or variant thereof is not included should not be taken as indication that particular algorithm is insecure.
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References
•Book
Handbook of Applied Cryptography
Alfred Menezes,Scott A. Vanstone,Paul C. van Oorschot +2 more
- 01 Jan 1996
TL;DR: A valuable reference for the novice as well as for the expert who needs a wider scope of coverage within the area of cryptography, this book provides easy and rapid access of information and includes more than 200 algorithms and protocols.
15K
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
TL;DR: This contribution investigates the significance of FPGA implementations of the Advanced Encryption Standard candidate algorithms, with a strong focus on high-throughput implementations, which are required to support security for current and future high bandwidth applications.
322
Unlocking the design secrets of a 2.29 Gb/s Rijndael processor
Patrick Schaumont,H. Kuo,Ingrid Verbauwhede +2 more
- 10 Jun 2002
TL;DR: This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput at 56 mw of power consumption.
AES Implementation on FPGA: Time - Flexibility Tradeoff
Anna Labbé,Annie Pérez +1 more
- 02 Sep 2002
TL;DR: This paper presents some FPGA-based implementations of the private key Advanced Encryption Standard (AES) cryptography algorithm that can ensure high speed encryption by processing several Blocks of the plaintext concurrently.
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