1. What contributions have the authors mentioned in the paper "An exact algorithm for selecting partial scan flip-flops" ?
This optimal solution was obtained in 32 CPU seconds on a SUN Sparc 2 workstation.
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An exact algorithm for selecting partial scan flip-flops
TL;DR: An exact algorithm for selecting partial scan flip-flops to break all feedback cycles to solve the MFVS problem exactly for large, practical instances is developed.
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Abstract: We develop anexact algorithm for selecting partial scan flip-flops to break all feedback cycles. We also permit the option of not breaking self-loops. The key ideas that allow us to solve this complex problemexactly for large, practical instances are—an MFVS-preserving graph transformation, a partitioning scheme used in the branch and bound procedure, and pruning techniques based on an integer linear programming formulation of the MFVS problem. We have obtained optimum solutions for all ISCAS'89 benchmark circuits and several production VLSI circuits within reasonable computation time. For example, the optimal number of scan flip-flops required to eliminate all cycles except self-loops in the circuit s38417 is 374. An optimal solution was obtained in 32 CPU seconds on a SUN Sparc 2 workstation.
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Citations
•Proceedings Article
Determining scan flip-flops in partial-scan designs
D. H. Lee,S. M. Reddy +1 more
- 02 Jan 1992
TL;DR: Results of applying optimal and heuristic procedures on a set of benchmark circuits indicate that heuristic methods give fast and near minimal solutions.
140
A layout-based approach for ordering scan chain flip-flops
S. Makar
- 18 Oct 1998
TL;DR: A new practical layout-based approach for ordering flip-flop scan chains is presented, which can reduce the stitching wire length by an order of magnitude, and dramatically improve circuit routability.
53
Trimodal Scan-Based Test Paradigm
TL;DR: The experimental results obtained for large and complex industrial application-specific IC designs illustrate the feasibility of the proposed test scheme despite additional costs and efforts entailed in consolidating architectural changes and operations across a DFT flow.
39
Partial scan design based on circuit state information
Dong Xiang,Srikanth Venkataraman,W. Kent Fuchs,Janak H. Patel +3 more
- 01 Jun 1996
TL;DR: Using valid states obtained via logic simulation, a testability measure based on the density of encoding is proposed and used to select scan flip flop selection and results are presented to demonstrate the effectiveness of the method.
39
Cost-free scan: a low-overhead scan path design methodology
Chih-Chang Lin,Mike Tien-Chien Lee,Malgorzata Marek-Sadowska,Kuang-Chien Chen +3 more
- 01 Dec 1995
TL;DR: A novel low-overhead scan design methodology is proposed, called cost-free scan, which exploits the controllability of primary inputs to establish scan paths through the combinational logic.
34
References
Combinatorial optimization: algorithms and complexity
TL;DR: This clearly written, mathematically rigorous text includes a novel algorithmic exposition of the simplex method and also discusses the Soviet ellipsoid algorithm for linear programming; efficient algorithms for network flow, matching, spanning trees, and matroids; the theory of NP-complete problems; approximation algorithms, local search heuristics for NPcomplete problems, more.
7.6K
A partial scan method for sequential circuits with feedback
TL;DR: A method of partial scan design is presented in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit.
353
On determining scan flip-flops in partial-scan designs
D.H. Lee,Sudhakar M. Reddy +1 more
- 11 Nov 1990
TL;DR: In this paper, the main idea pursued is to derive a minimal feedback vertex set of the so-called S-graphs, which is then used to determine flip-flops to be scanned in partial-scan designs for sequential circuits.
234
The Ballast methodology for structured partial scan design
Rajiv Gupta,Melvin A. Breuer +1 more
TL;DR: An efficient partial scan technique called Ballast (balanced structure scant test) is presented, which leads to a low area overhead and allows 100% coverage of irredundant faults.
186
An Exact Algorithm for Selecting Partial Scan Flip-Flops
Srimat T. Chakradhar,Arun Balakrishnan,Vishwani D. Agrawal +2 more
- 06 Jun 1994
TL;DR: An exact algorithm for selecting flip-flops in partial scan designs to break all feedback cycles and obtaining optimum solutions for the ISCAS '89 benchmark circuits and several production VLSI circuits within reasonable computation time is developed.