Journal Article10.1145/63404.63407
An analytical cache model
354
TL;DR: An analytical cache model is developed that gives miss rates for a given trace as a function of cache size, degree of associativity, block size, subblock size, multiprogramming level, task switch interval, and observation interval.
read more
Abstract: Trace-driven simulation and hardware measurement are the techniques most often used to obtain accurate performance figures for caches. The former requires a large amount of simulation time to evaluate each cache configuration while the latter is restricted to measurements of existing caches. An analytical cache model that uses parameters extracted from address traces of programs can efficiently provide estimates of cache performance and show the effects of varying cache parameters. By representing the factors that affect cache performance, we develop an analytical model that gives miss rates for a given trace as a function of cache size, degree of associativity, block size, subblock size, multiprogramming level, task switch interval, and observation interval. The predicted values closely approximate the results of trace-driven simulations, while requiring only a small fraction of the computation cost.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
•Book
Memory Systems: Cache, DRAM, Disk
Bruce Jacob,Spencer W. Ng,David T. Wang +2 more
- 10 Sep 2007
TL;DR: Is your memory hierarchy stopping your microprocessor from performing at the high level it should be?
813
Predicting inter-thread cache contention on a chip multi-processor architecture
Dhruba Chandra,Fei Guo,Seongbeom Kim,Yan Solihin +3 more
- 12 Feb 2005
TL;DR: Three performance models are proposed that predict the impact of cache sharing on co-scheduled threads and the most accurate model, the inductive probability model, achieves an average error of only 3.9%.
Patent
Integrated circuit I/O using a high performance bus interface
Michael Farmwald,Mark Horowitz +1 more
- 16 Apr 1991
TL;DR: In this article, the authors present a memory subsystem comprising at least two semiconductor devices (15, 16, 17), including at least one memory device connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address.
552
A Comprehensive Survey of Network Function Virtualization
TL;DR: A comprehensive survey on NFV is presented, which starts from the introduction of NFV motivations, and provides an extensive and in-depth discussion on state-of-the-art VNF algorithms including VNF placement, scheduling, migration, chaining and multicast.
524
A new memory monitoring scheme for memory-aware scheduling and partitioning
G.E. Suh,Srinivas Devadas,Larry Rudolph +2 more
- 02 Feb 2002
TL;DR: A scheme that enables an accurate estimate of the isolated miss-rates of each process as a function of cache size under the standard LRU replacement policy is described, which can be used to schedule jobs or to partition the cache to minimize the overall miss-rate.
References
Cache Memories
TL;DR: Specific aspects of cache memories investigated include: the cache fetch algorithm (demand versus prefetch), the placement and replacement algorithms, line size, store-through versus copy-back updating of main memory, cold-start versus warm-start miss ratios, mulhcache consistency, the effect of input /output through the cache, the behavior of split data/instruction caches, and cache size.
1.6K
Evaluation techniques for storage hierarchies
TL;DR: A new and efficient method of determining, in one pass of an address trace, performance measures for a large class of demand-paged, multilevel storage systems utilizing a variety of mapping schemes and replacement algorithms.
1.4K
Using cache memory to reduce processor-memory traffic
James R. Goodman
- 13 Jun 1983
TL;DR: It is demonstrated that a cache exploiting primarily temporal locality (look-behind) can indeed reduce traffic to memory greatly, and introduce an elegant solution to the cache coherency problem.
Principles of Optimal Page Replacement
TL;DR: A formal model is presented for paging algorithms under /-order nonstationary assumptions about program behavior that is expressed as a dynamic programming problem whose solution yields an optimal replacement algorithm.
320
Related Papers (5)
[...]
John L. Hennessy,David A. Patterson +1 more
- 01 Dec 1989