Proceedings Article10.1109/ICCAD.1991.185200
An algorithm for component selection in performance optimized scheduling
L. Ramachandran,D.D. Gajski +1 more
- 11 Nov 1991
- pp 92-95
53
TL;DR: A novel algorithm is described that combines the hardware scheduling and component selection phases for high level synthesis, by being able to simultaneously select components from a given library, which enlarges the design space, resulting in better optimized designs.
read more
Abstract: The authors describe a novel algorithm that combines the hardware scheduling and component selection phases for high level synthesis. The algorithm improves on previous work in scheduling, by being able to simultaneously select components from a given library. This enlarges the design space, resulting in better optimized designs. Experimental results on the elliptic filter benchmark demonstrate that exploiting all available components in the library results in designs with smaller area compared to designs produced by scheduling with a single implementation for each component type. >
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Partitioning and pipelining for performance-constrained hardware/software systems
S. Bakshi,Daniel D. Gajski +1 more
TL;DR: The ability to incorporate partitioning with pipelining at several levels of granularity enables the author to attain high throughput designs, and also distinguishes this paper from previously proposed hardware/software partitioning algorithms.
72
Execution interval analysis under resource constraints
A.H. Timmer,Jochen A. G. Jess +1 more
- 07 Nov 1993
TL;DR: A novel and much more accurate execution interval analysis is presented for designs on which resource constraints are imposed that prunes the search space of schedulers without limiting the solution space and therefore enhances the quality of Schedulers.
48
Functional synthesis of digital systems with TASS
S. Amellal,Bozena Kaminska +1 more
TL;DR: The Tabu Search technique, which performs an intelligent and fast solution space exploration, combined with an effective mathematical formulation makes the scheduling algorithm presented here very powerful.
47
Module selection and scheduling using unrestricted libraries
A.H. Timmer,M.J.M. Heijligers,L. Stok,Jochen A. G. Jess +3 more
- 22 Feb 1993
TL;DR: A module selection and scheduling approach which allows the full use of unrestricted libraries and clearly illustrates the advantages of synthesis tools which can fully cope with unrestricted libraries, as they lead to designs with less module area.
45
A memory selection algorithm for high-performance pipelines
Smita Bakshi,Daniel D. Gajski +1 more
- 01 Dec 1995
TL;DR: This paper presents an algorithm to select a memory organization, in addition to selecting a pipeline and other datapath components, given performance constraints, and conducts experiments to give a quantitative measure of the impact of memory selection on DSP design.
35
References
Automated Synthesis of Data Paths in Digital Systems
TL;DR: This paper presents a unifying procedure, called Facet, for the automated synthesis of data paths at the register-transfer level that minimizes the number of storage elements, data operators, and interconnection units.
584
Automated synthesis of data paths in digital systems (design space)
Chia-Jeng Tseng
- 01 Jan 1984
TL;DR: In this paper, the problem of data-memory allocation includes five subtasks: specification of data flow and control flow, allocation of storage elements, data operators, the allocation of interconnection units, and the exploration of a design space.
344
Scheduling and Binding Algorithms for High-Level Synthesis
P. G. Paulin,J.P. Knight +1 more
- 01 Jun 1989
TL;DR: New algorithms for high-level synthesis are presented and a clique partitioning approach is used where the clique graph is pruned using interconnect affinities between register (bus) pairs.
165