Journal Article10.11591/IJINS.V1I2.530
AES Encryption Algorithm Hardware Implementation Architecture: Resource and Execution Time Optimization
Samir El Adib,Naoufal Raissouni +1 more
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TL;DR: An architecture to implement Advanced Encryption Standard (AES) Rijndael algorithm in reconfigurable hardware in FPGA that can be used in a wide range of embedded applications is presented and compared with other reference implementations.
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Abstract: In the present paper we present an architecture to implement Advanced Encryption Standard (AES) Rijndael algorithm in reconfigurable hardware. Rijndael algorithm is the new AES adopted by the National Institute of Standards and Technology (NIST) to replace existing Data Encryption Standard (DES). Compared to software implementation, hardware implementation of Rijndael algorithm provides more physical security as well as higher speed. The first factor to be considered on implementing AES is the application. High-speed designs are not always desired solutions. In some applications, such as mobile computing and wireless communications, smaller throughput is demanded. Architecture presented uses memory modules (i.e., Dual-Port RAMs) of Field-Programmable Gate Array (FPGAs) for storing all the results of the fixed operations (i.e., Look-Up Table), and Digital Clock Manager (DCM) that we used effectively to optimize the execution time, reduce design area and facilitates implementation in FPGA. The architecture consumes only 326 slices plus 3 Block Random Access Memory (BRAMs). The throughput obtained was of 270 Mbits/s. The target hardware used in this paper is Spartan XC3S500E FPGA from Xilinx. Results are presented and compared with other reference implementations, as known from the technical literature. The presented architecture can be used in a wide range of embedded applications.
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Citations
FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm
TL;DR: The architecture of the AES algorithm is implemented in the gate level by high-speed and breakable structures that are desirable for the 2-slow retiming that achieves a high throughput of 86Gb/s and high maximum operation frequency of 671.524MHz.
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An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box
TL;DR: An efficient structural architecture is proposed for AES Encryption process to achieve high throughput with less device utilization and the results are analysed, throughput and area for the implemented design are calculated.
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•Journal Article
Single-chip FPGA implementation of the advanced encryption standard algorithm
M. McLoone,John V. McCanny +1 more
TL;DR: The FPGA implementation described here is that of a fully pipelined single-chip Rijndael design which runs at a data rate of 7 Gbits/sec on a Xilinx Virtex-E XCV812E-8-BG560 FPGAs device, which proves to be one of the fastest single- chip RIJndael implementations currently available.
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Dynamic Partial Reconfiguration Implementation of AES Algorithm
Snehal Wankhade,Rashmi Mahajan +1 more
TL;DR: Partial Reconfiguration by which selected areas of an FPGA can be reconfigured during runtime could be a good solution to preserve confidentiality and convenience to the information in the numeric communication.
An AES cryptosystem for small scale network
Ukrit Arom-oon
- 01 Jan 2017
TL;DR: The Advanced Encryption standard (AES) cryptosystem for the small scale network presents the implementation of the AES algorithm, FIPS 197, on the microcontroller operated on the real-time operating system (RTOS) for securing data in a small scalenetwork for example as an UAVs wireless communication.
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Xinmiao Zhang,Keshab K. Parhi +1 more
TL;DR: Using the proposed architecture, a fully subpipelined encryptor with 7 substages in each round unit can achieve a throughput of 21.56 Gbps on a Xilinx XCV1000 e-8 bg560 device in non-feedback modes, which is faster and 79% more efficient in terms of equivalent throughput/slice than the fastest previous FPGA implementation known to date.
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Alex Biryukov,Christophe De Cannière +1 more
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Pawel Chodowiec,Kris Gaj +1 more
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TL;DR: Specific features of Spartan II FPGAs enabling compact logic implementation are explored, and a new way of implementing MixColumnsand InvMixColumnstransformations using shared logic resources is presented.
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
TL;DR: This contribution investigates the significance of FPGA implementations of the Advanced Encryption Standard candidate algorithms, with a strong focus on high-throughput implementations, which are required to support security for current and future high bandwidth applications.
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