Aer-srt

TL;DR: This contribution intends to provide a tool that allows to prototype SNNs faster than on CPU/GPU architectures but significantly cheaper than fabricating a customized neuromorphic chip.

TL;DR: The design of the multiplier was inspired by the biological processes of dendrites, which use feedback connections and dendritic growth to synchronize the neural processing performed by the soma to increase processing speed compared with previously reported solutions based on Spiking Neural Networks.

TL;DR: This paper develops a novel parallel multiplier that is based on spiking neural P systems and is capable of multiplying two natural numbers with many digits in parallel and employs the divide and conquer strategy to optimize the processing time of the arithmetic operations.

TL;DR: The results demonstrate that the neuromorphic architecture is capable of processing higher adaptive FIR filters compared with previously reported solutions and potentially allow its practical use in many advanced digital signal processing applications such as acoustic echo cancellers, active noise control, channel equalization and system identification.

TL;DR: A minimal spiking network that can polychronize, that is, exhibit reproducible time-locked but not synchronous firing patterns with millisecond precision, as in synfire braids is presented.

TL;DR: SpiNNaker as discussed by the authors is a massively parallel million-core computer whose interconnect architecture is inspired by the connectivity characteristics of the mammalian brain, and which is suited to the modeling of large-scale spiking neural networks in biological real time.

TL;DR: The current state of the spiking neural network architecture project is reviewed, and the real-time event-driven programming model that supports flexible access to the resources of the machine and has enabled its use by a wide range of collaborators around the world is presented.

TL;DR: It is demonstrated that a spiking neuron algorithm can be efficiently mapped to Bluehive using Bluespec System Verilog by taking a communication-centric approach, which contrasts with many FPGA-based neural systems which are very focused on parallel computation, resulting in inefficient use of FPGAs.