Patent
Address conversion unit for data processing system
Tadaaki Bandoh,Fukunaga Yasushi +1 more
- 25 Sep 1978
19
TL;DR: In this article, an address conversion method and unit for a data processing system is disclosed which converts logical addresses into physical addresses representative of plural addressable storage locations, each instruction includes a portion indicative of a first or second kind of instruction.
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Abstract: An address conversion method and unit for a data processing system is disclosed which converts logical addresses into physical addresses representative of plural addressable storage locations. Each instruction includes a portion indicative of a first or second kind of instruction. In the case where an instruction is of the first kind, the content of a register in a first base register arrangement specified by the instruction is added with an address part of the instruction to produce a logical address. In the case where an instruction is of the second kind, on the other hand, the content of a register in a second base register arrangement specified by the instruction different from the first base register arrangement is juxtaposed with an address part of the instruction to produce a logical address.
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Citations
Patent
Memory management unit
John Zolnowsky,Charles L. Whittington,William M. Keshlear +2 more
- 14 Dec 1981
TL;DR: In this article, an improved associative memory circuit is proposed to detect mapping conflicts between new segment descriptors and existing descriptors, and to prevent the storage of such conflicting segments descriptors.
83
Patent
Interleaved memory access system having variable-sized segments logical address spaces and means for dividing/mapping physical address into higher and lower order addresses
Steve S. Chen,Frederick J. Simmons,George A. Spix,Jimmie R. Wilson,Edward C. Miller,Roger E. Eckert,Douglas R. Beard +6 more
- 29 Jun 1994
TL;DR: In this paper, a method of accessing common memory in a cluster architecture for a highly parallel multiprocessor scaler/factor computer system using a plurality of segment registers in which a logical address is within a start and end range as defined by the segment registers and then relocating the logical address to a physical address using a displacement value in another segment register.
66
Patent
Virtual memory management and allocation arrangement for digital data processing system
Gary H. Newman,James W. Franklin +1 more
- 11 Mar 1991
TL;DR: In this paper, a table that associates segments of the virtual address space with predetermined array data dimensions and maintains a map that identifies, for each segment, which portions of the segment have been allocated to store array data.
53
Patent
Computer system having mode independent addressing
Richard Bealkowski,Dayan Richard Alan,David Joseph Doria,Kinnear Scott Gerard,Jeffrey I Krantz,Liverman Robert B,Guy G. Sotomayor,Donald D Williams,Gary Anthony Vaiskauckas +8 more
- 27 Mar 1987
TL;DR: In this paper, a computer system and a method for operating in mutually incompatible real and protected addressing modes, in which programs written for one mode can be run in the other mode without modification, is presented.
47
Patent
Virtual memory management arrangement for addressing multi-dimensional arrays in a digital data processing system
Gary H. Newman
- 29 Jul 1991
TL;DR: In this article, a virtual address translation portion forms, in response to a process virtual address, an array virtual address including a sub-array identifier identifying a subarray in the array, and a virtual offset identifying a virtual storage location in the subarray.
47
References
Patent
Instruction translation control with extended address prefix decoding
John E. Mekota,M. Hudson David,G. Rankin Thomas,E. Champagne Jean +3 more
- 06 Oct 1970
TL;DR: A special purpose prefix is defined which replaces the normal opcode field of an instruction, having the effect of translating that instruction from a normal instruction into an instruction with various formate extensions in addresses, indices and/or augments as discussed by the authors.
68
Patent
Word, byte and bit indexed addressing in a data processing system
William E. Woods,Philip E. Stanley +1 more
- 07 Apr 1976
TL;DR: In this article, a data processing system for providing word, byte or bit addressing is presented, where a word location in a memory device may be addressed based upon the contents of a base address register and indirect addressing may be provided to another word location based upon a word index value in an index register.
31
Patent
Microprocessor with immediate and indirect addressing
Richard A. Garlic
- 26 Dec 1973
TL;DR: In this paper, a microprocessor with a bus structure for carrying address and data signals wherein an address may be modified by an index value for indirect addressing by deriving said index value from an index register or a control word field is presented.
22
Patent
Method of generating addresses to a paged memory
Garvin Wesley Patterson,Marion G. Porter +1 more
- 26 Mar 1975
TL;DR: In this paper, an input-output processing system which performs communication and control functions in a larger data processing system includes a processor for address development to paged memory and program instruction execution for I/O command sequences.
22
Patent
Random access memory apparatus for a waveform measuring apparatus
Steven R. Smith,Frederick A. Rose +1 more
- 26 Mar 1976
TL;DR: In this article, the direction memory is written by the processor in accordance with the setting of a user operated control means for selection of the memory configuration, which can be configured or organized as one single memory section, two individual half sections, or four individual sections.
20