Journal Article10.1016/J.MICPRO.2014.03.011
Accelerating image boundary detection by hardware parallelism
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TL;DR: A promising way to improve the real-time performance of high-quality image boundary detection systems, especially when embedded and real- time systems are taken into account is demonstrated.
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About: This article is published in Microprocessors and Microsystems. The article was published on 01 Jul 2014. The article focuses on the topics: Hardware acceleration & Boundary (topology).
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Citations
Suitability of recent hardware accelerators (DSPs, FPGAs, and GPUs) for computer vision and image processing algorithms
TL;DR: The practical details of chip architectures, available tools and utilities, development time, and the relative advantages and disadvantages of using DSPs, FPGAs, and GPUs are discussed.
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A Real-Time FPGA Based Human Detector
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TL;DR: This study has proven that the reduction on the total detection rate is less than 0.3% while changing HOG algorithm into the presented FPGA hardware implementation.
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High-Throughput, Resource-Efficient Multi-Dimensional Parallel Architecture for Space-Borne Sea-Land Segmentation
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