Proceedings Article10.1109/ISCAS.2003.1206232
A zero-time-overhead asynchronous four-phase controller
Nattha Sretasereekul,Hiroshi Saito,Masashi Imai,Euiseok Kim,M. Ozcan,K. Thongnoo,Hiroshi Nakamura,Takashi Nanya +7 more
- 25 May 2003
- Vol. 5, pp 205-208
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TL;DR: A new interface is introduced so that area overhead of matched delay elements and control time overhead of the four-phase handshake protocol can be reused as a part of the matched delay, and the time overhead can be zero and the amount of components used for composing the matcheddelay can be dramatically reduced.
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Abstract: Asynchronous single-rail datapath implementations turn out to be superior to the dual-rail implementations in some dimensions; they consume less energy and require less circuit area. However, there still exist area overhead of matched delay elements and control time overhead of the four-phase handshake protocol. In this paper, we introduce a new interface so that such time overhead can be reused as a part of the matched delay. Consequently, the time overhead can be zero, and the amount of components used for composing the matched delay can be dramatically reduced. The larger the control time overhead is, the smaller the delay chain becomes. The full performance and low-power advantages of asynchronous circuits can be obtained. We demonstrate this on a single-rail differential equation solver.
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Citations
High level synthesis of timed asynchronous circuits
Tomohiro Yoneda,A. Matsumoto,M. Kato,Chris J. Myers +3 more
- 14 Mar 2005
TL;DR: The experiments to synthesize a portion of a DCT circuit show that the proposed method can handle a nontrivial example and produce a smaller and faster circuit than a previous approach.
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Patent
Asynchronous ripple pipeline
Paul Wielage
- 04 Sep 2006
TL;DR: An asynchronous ripple pipeline has a plurality of stages, each with a controller (18) and a register (16), each having a register control output (21), and a combined acknowledgement and request output (20), together with a request input (22) and an acknowledgement input (24) as discussed by the authors.
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Asynchronous pipeline controller based on early acknowledgement protocol
Chammika Mannakkara,Tomohiro Yoneda +1 more
- 23 Jun 2008
TL;DR: A new asynchronous pipeline controller based on early acknowledgement protocol, which indicates acknowledgment by the falling edge of the acknowledgment signal, and thus, it can hide the overhead caused by a resetting phase of the handshake cycle, is proposed.
Synthesis of Timed Circuits Based on Decomposition
Tomohiro Yoneda,Chris J. Myers +1 more
TL;DR: This paper presents a decomposition-based method for timed circuit design that is capable of significantly reducing the cost of synthesis and can be applied to find circuits for which full-state-space methods cannot be successfully applied.
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Synthesis of locally-clocked asynchronous systems with bundled-data implementation on FPGAs
Kledermon Garcia,Duarte L. Oliveira,Tiago Curtinhas,Roberto d'Amore +3 more
- 01 Nov 2014
TL;DR: This new method proposes to design asynchronous FSM with local clock and uses the extended burst-mode specification to describe the controller and shows an average performance increase with an average area increase of 27% LUTs, when compared with synchronous versions.
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References
•Book
Synthesis and optimization of digital circuits
Giovanni De Micheli
- 01 Jan 1994
TL;DR: This book covers techniques for synthesis and optimization of digital circuits at the architectural and logic levels, i.e., the generation of performance-and-or area-optimal circuits representations from models in hardware description languages.
•Dissertation
Synthesis of self-timed vlsi circuits from graph-theoretic specifications
T. Chu
- 01 Jun 1987
TL;DR: This thesis presents an approach for direct and efficient synthesis of self-timed (asynchronous) control circuits from formal specifications called Signal Transition Graphs (STGs), and develops a number of analytical results which establish the equivalence between the static structure of nets and their underlying firing sequence semantics.
554
A fast asynchronous Huffman decoder for compressed-code embedded processors
R. Benes,Steven M. Nowick,Andrew Wolfe +2 more
- 30 Mar 1998
TL;DR: The architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors is presented, estimated to have higher throughput than any comparable synchronous HuffmanDecoder (after normalizing for feature size and voltage), yet is much smaller than synchronous designs.
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In: "1998 IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems" ("Async98" Symposium),San Diego,CA A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors
M. Nowick,Andrew Wolfe +1 more
- 01 Jan 1998
TL;DR: In this article, the authors present the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors, which is implemented as an iterative self-timed ring.
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