Proceedings Article10.1145/1016568.1016614
A VLIW low power Java processor for embedded applications
Antonio Carlos Schneider Beck,Luigi Carro +1 more
- 04 Sep 2004
- pp 157-162
31
TL;DR: This paper shows that, thanks to the specific stack architecture and to the use of the VLIW technique, one is able to obtain a meaningful reduction of power dissipation, with small area overhead, when compared to other ways of executing Java in hardware.
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Abstract: This paper presents a pioneer VLIW architecture of a native Java processor. We show that, thanks to the specific stack architecture and to the use of the VLIW technique, one is able to obtain a meaningful reduction of power dissipation, with small area overhead, when compared to other ways of executing Java in hardware. The underlying technique is based on the reuse of memory access instructions, hence reducing power during memory or cache accesses. The architecture is validated for some complex embedded applications like IMDCT computation and other data processing benchmarks.
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Power analysis of embedded software: a first step towards software power minimization
TL;DR: A power analysis technique is developed that has been applied to two commercial microprocessors and can be employed to evaluate the power cost of embedded software and can help in verifying if a design meets its specified power constraints.
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A 160 MHz 32 b 0.5 W CMOS RISC microprocessor
J. Montanaro,R. Witek,K. Anne,A.J. Black,Elizabeth M. Cooper,Daniel W. Dobberpuhl,P. Donahue,J. Eno,A. Farell,G. Hoeppner,D. Kruckemyer,Thomas H. Lee,P. Lin,L. Madden,Daniel C. Murray,M. Pearce,S. Santhanam,K. Snyder,R. Stephany,S.C. Thierauf +19 more
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TL;DR: This custom VLSI implementation of a microprocessor architecture delivers 184 Drystone/MIPS at 162 MHz dissipating 0.5 W using an 1.5 V internal supply and Clock generation uses an on-chip PLL with 3.68 MHz input clock to minimize high frequency clock signals on the board.
733
A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
James Montanaro,Richard T. Witek,Krishna Anne,Andrew J. Black,Elizabeth M. Cooper,Daniel W. Dobberpuhl,Paul M. Donahue,Jim Eno,Gregory W. Hoeppner,David A. Kruckemyer,Thomas H. Lee,Peter C. M. Lin,Liam Madden,Daniel C. Murray,Mark H. Pearce,Sribalan Santhanam,Kathryn J. Snyder,Ray Stephany,Stephen C. Thierauf +18 more
TL;DR: A 160 MHz 500 mW 32 b StrongARM(R) microprocessor designed for low-power, low-cost applications that implements the ARM(R) V4 instruction set and is bus compatible with earlier implementations is described.
435
picoJava-I: the Java virtual machine in hardware
J.M. O'Connor,Marc Tremblay +1 more
TL;DR: This small, flexible microprocessor core provides performance five to 20 times better than other means of Java execution and the microarchitecture trade-offs made for picoJava-I are illustrated.
170