Proceedings Article10.1109/DELTA.2008.76
A Visual Notation for Processor and Resource Scheduling
C.T. Johnston,Paul Lyons,Donald G. Bailey +2 more
- 03 Mar 2008
- pp 296-301
TL;DR: A number of graphical representations for scheduling which were evaluated for use in a visual language for image processing on FPGAs are proposed and their strengths and weakness discussed and the reasons for adoption of the state chart notation are given.
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Abstract: Scheduling of concurrent processors in a real-time image processing system on FPGA (field programmable gate array) hardware is a not a trivial task. We propose a number of graphical representations for scheduling which were evaluated for use in a visual language for image processing on FPGAs. The proposed representations are illustrated and their strengths and weakness discussed and the reasons for adoption of the state chart notation are given.
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Citations
User evaluation and overview of a visual language for real time image processing on FPGAs
C.T. Johnston,Paul Lyons,Donald G. Bailey +2 more
- 06 Jul 2009
TL;DR: The paper presents the results of two user evaluations of VERTIPH, a pre-implementation paper-based user evaluation which found no major changes were required and a post-(partial)-implementation user evaluation, which evaluated the novel parts of the language using participants experienced in the field.
4
Notations for Multiphase Pipelines
C.T. Johnston,Donald G. Bailey,Paul Lyons +2 more
- 13 Jan 2010
TL;DR: This paper shows how many of these problems may be overcome by basing the notation on sequential dataflow, and discusses control issues of priming, stalling and flushing, with a proposed compiler implementation.
1
Design Constraints
Donald G. Bailey
- 05 Sep 2023
TL;DR: Design constraints include timing, memory bandwidth, resource, and power constraints. These constraints are mapped onto the FPGA during the implementation process.
References
Statecharts: A visual formalism for complex systems
TL;DR: It is intended to demonstrate here that statecharts counter many of the objections raised against conventional state diagrams, and thus appear to render specification by diagrams an attractive and plausible approach.
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Usability Analysis of Visual Programming Environments: A 'Cognitive Dimensions' Framework
Thomas R. G. Green,Marian Petre +1 more
TL;DR: This paper applies the cognitive dimensions framework to two commercially-available dataflow languages and concludes that it is effective and insightful; other HCI-based evaluation techniques focus on different aspects and would make good complements.
System Deadlocks
TL;DR: This article surveys the work that has been done on the treatment of deadlocks from both the theoretical and practical points of view.
845
The Khoros software development environment for image and signal processing
TL;DR: This paper presents a general overview of Khoros with emphasis on its image processing and DSP tools.
259
Novel FPGA-based implementation of median and weighted median filters for image processing
Suhaib A. Fahmy,Peter Y. K. Cheung,Wayne Luk +2 more
- 10 Oct 2005
TL;DR: An efficient hardware implementation of a median filter is presented, which offers a realisable way of efficiently implementing large-windowed median filtering, as required by transforms such as the Trace Transform.
86