How many cycles is the synchronous DRAM in the first column?

For the synchronous DRAM (SDRAM) in the forth column, a latency of 5 cycles (3 cycle for the row address and 2 cycle CAS latency) is assumed.

Why is the instruction cache ignored on all other instructions?

Due to the fact that all cache misses are included in two instructions (invoke and return) only, the instruction cache can be ignored on all other instructions.

What is the benchmark for simulating the real-world workload?

A simulation of the environment (sensors and actors) and the communication system (commands from the master station) forms part of the benchmark for simulating the real–world workload.

How many times did the major loop of the application run?

During this time, the major loop of the application was executed several hundred times, effectively rendering any misses during the initialization code irrelevant to the measurements.

What is the memory size for a block size of 8 bytes?

Although the SRAM has half the bandwidth of the SDRAM and a quarter of the DDR, with a block size of 8 bytes it is faster than the DRAM memories.

What is the way to analyze a WCET value?

Avoiding or ignoring this feature in real–time systems, due to its unpredictable behavior, results in a very pessimistic WCET value.

What is the main disadvantage of a single method cache?

In a conventional cache design, if these three methods can be fitted in the cache memory at the same time and there is no placement conflict, each method is only loaded once.

What is the impact of the instruction cache on WCET analysis?

Plenty of effort has gone into research into integrating the instruction cache in the timing analysis of tasks [2, 3] and the cache’s influence on task preemption [4, 5].

How many blocks are the fastest solution for a memory?

In most cases a block size of 16 bytes is the fastest solution and the authors will therefore use this configuration for comparison with the following cache solutions.

What is the difference between the tag and the LRU memory?

this memory can be slower than the tag memory as it is only accessed on invocation or return, rather than on every cache access.

How many methods are in the variable block cache?

From the gap between 16 and 32 blocks (within the 4 KB cache), the authors can say that the application consists of fewer than 32 different methods.

Open AccessBook Chapter10.1007/978-3-540-30470-8_52

A Time Predictable Instruction Cache for a Java Processor

Martin Schoeberl

- 25 Oct 2004

- pp 371-382

TL;DR: This paper proposes a different cache architecture, intended to ease WCET analysis, where the cache stores complete methods and cache misses occur only on method invocation and return.

Abstract: Cache memories are mandatory to bridge the growing gap between CPU speed and main memory access time. Standard cache organizations improve the average execution time but are difficult to predict for worst case execution time (WCET) analysis. This paper proposes a different cache architecture, intended to ease WCET analysis. The cache stores complete methods and cache misses occur only on method invocation and return. Cache block replacement depends on the call tree, instead of instruction addresses.

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1. What are the contributions mentioned in the paper "A time predictable instruction cache for a java processor" ?

This paper proposes a different cache architecture, intended to ease WCET analysis.

2. What is the effect of smaller blocks on the memory?

With smaller block sizes, the chance of unused data being read is reduced and the larger number of blocks reduces conflict misses.

3. How is the time needed to load a complete method calculated?

The time needed to load a complete method is calculated using the memory properties (latency and bandwidth) and the length of the method.

4. What is the worst case scenario for a cache stall?

The worst case scenario for the memory stall time for an instruction fetch or a data load is two miss penalties when both cache reads are a miss.

Table 5.Direct–mapped cache, average memory access time

Table 3.Stack oriented replacement policy

Table 9.Variable block cache, average memory access time

Citations

•Journal Article•10.1016/J.SYSARC.2007.06.001

A Java processor architecture for embedded real-time systems

Martin Schoeberl

- 01 Jan 2008

- Journal of Systems Architecture

TL;DR: It is demonstrated that a hardware implementation of the Java virtual machine results in a small design for resource-constrained devices.

...read moreread less

250

•Book

On The Move to meaningful Internet systems 2003 : OTM 2003 Workshops : OTM Confederated International Workshops : HCI-SWWA, IPW, JTRES, WORM, WMS, and WRSM 2003, Catania, Sicily, Italy, November 3-7, 2003 : proceedings

Robert Meersman, +6 more

- 01 Jan 2003

TL;DR: In this article, the authors exploit the experiences with Jironde, a flexible framework that extends the Fractal component model with transactions via a set of transactional controllers that manage transactions on behalf of a component, identifying several key architectural and technical issues related to enhancing component-based middleware with transactions.

...read moreread less

205

•Book

JOP: A Java Optimized Processor for Embedded Real-Time Systems

Martin Schoeberl

- 30 Jun 2008

TL;DR: This thesis presents a Java processor designed for time-pre dictable execution of real-time tasks and introduces a processor architectur in which simpler and more accurate WCET analysis is more important than average case p erformance.

...read moreread less

167

•10.4230/OASICS.PPES.2011.11

Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

Martin Schoeberl, +6 more

- 18 Mar 2011

TL;DR: This paper presents Patmos, a processor optimized for low WCET bounds rather than high average case performance, a dual- issue, statically scheduled RISC processor that relies on a customized compiler.

...read moreread less

114

...

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References

•Book

Computer Architecture: A Quantitative Approach

John L. Hennessy, +1 more

- 01 Dec 1989

TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.

...read moreread less

12.6K

Journal Article•10.1109/12.689649

Analysis of cache-related preemption delay in fixed-priority preemptive scheduling

Chang-Gun Lee, +8 more

- 01 Jun 1998

- IEEE Transactions on Computers

TL;DR: The results show that the proposed approach gives a prediction of the worst case cache-related preemption delay that is up to 60 percent tighter than those obtained from the previous approaches.

...read moreread less

308

Journal Article•10.1109/JPROC.2003.814618

The influence of processor architecture on the design and the results of WCET tools

Reinhold Heckmann, +3 more

- 28 Jul 2003

TL;DR: The designs of WCET tools for a series of increasingly complex processors, including SuperSPARC, Motorola ColdFire 5307, and Motorola PowerPC 755, are described, and some advice is given as to the predictability of processor architectures.

...read moreread less

287

•Book

On The Move to meaningful Internet systems 2003 : OTM 2003 Workshops : OTM Confederated International Workshops : HCI-SWWA, IPW, JTRES, WORM, WMS, and WRSM 2003, Catania, Sicily, Italy, November 3-7, 2003 : proceedings

Robert Meersman, +6 more

- 01 Jan 2003

...read moreread less

205

Proceedings Article•10.1109/RTTAS.1996.509537

Adding instruction cache effect to schedulability analysis of preemptive real-time systems

J.V. Busquets-Mataix, +4 more

- 10 Jun 1996

TL;DR: The paper describes how to incorporate the effect of instruction cache to the Response Time schedulability Analysis (RTA), an efficient analysis for preemptive fixed priority schedulers and compares the results of such an approach to both cache partitioning and CRMA.

...read moreread less

193

A Time Predictable Instruction Cache for a Java Processor

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AI Agents for this Paper

Most frequently asked questions

1. What are the contributions mentioned in the paper "A time predictable instruction cache for a java processor" ?

2. What is the effect of smaller blocks on the memory?

3. How is the time needed to load a complete method calculated?

4. What is the worst case scenario for a cache stall?

5. How many cycles is the synchronous DRAM in the first column?

6. Why is the instruction cache ignored on all other instructions?

7. What is the benchmark for simulating the real-world workload?

8. How many times did the major loop of the application run?

9. What is the memory size for a block size of 8 bytes?

10. What is the way to analyze a WCET value?

11. What is the main disadvantage of a single method cache?

12. What is the impact of the instruction cache on WCET analysis?

13. How many blocks are the fastest solution for a memory?

14. What is the difference between the tag and the LRU memory?

15. How many methods are in the variable block cache?

Figures

Citations

A Java processor architecture for embedded real-time systems

T-crest

On The Move to meaningful Internet systems 2003 : OTM 2003 Workshops : OTM Confederated International Workshops : HCI-SWWA, IPW, JTRES, WORM, WMS, and WRSM 2003, Catania, Sicily, Italy, November 3-7, 2003 : proceedings

JOP: A Java Optimized Processor for Embedded Real-Time Systems

Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

References

Computer Architecture: A Quantitative Approach

Analysis of cache-related preemption delay in fixed-priority preemptive scheduling

The influence of processor architecture on the design and the results of WCET tools

On The Move to meaningful Internet systems 2003 : OTM 2003 Workshops : OTM Confederated International Workshops : HCI-SWWA, IPW, JTRES, WORM, WMS, and WRSM 2003, Catania, Sicily, Italy, November 3-7, 2003 : proceedings

Adding instruction cache effect to schedulability analysis of preemptive real-time systems

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