A static-placement, dynamic-issue framework for CGRA loop accelerator

TL;DR: C-Map improves the effectiveness of CGRA mapping in the perspective of reducing network congestion and enhancing the continuity of the data-flow and analyzes the impact of several key considerations in CGRA instruction mapping, such as NoC workload reduction and workload balance.

TL;DR: This paper summarizes the latest progress in key technologies of dynamically reconfigurable computing and provides an introduction of the application achievements.

TL;DR: In this article, an architectural efficiency metric that quantifies the number of instructions or the size of reconfiguration bits required to perform a computation over a range of program sizes in the architecture is proposed.

Abstract: Coarse-Grained Reconfigurable Architectures (CGRAs) have been regarded as promising spatial computing fabric for the ever-evolving algorithms in multiple domains. However, pure software scheduling cannot compensate for the deficiencies in over-serialization and load imbalancing of these pure static CGRA designs. To address the issues caused by limited hardware flexibility, an in-depth study on the balance between the software and hardware scheduling design of CGRA is needed to achieve more precise, accurate, and adaptive scheduling of dataflow. In this paper, we propose DFGAS ( DFG - A ware S cheduling), a dataflow-driven CGRA which provides a comprehensive scheduling approach that encompasses software prediction, runtime adaptive execution, and post-execution refinement. Prior to execution, the TimeStamp prediction algorithm, coupled with the inherent dataflow execution model, enables coarse-grained (block-level) prediction for prioritized transfer and computation on NoC and PEs. During execution, the execution of key dataflow graph (DFG) blocks and edges is accelerated by incorporating a dynamic and adaptive dataflow mechanism. It leverages hardware-software co-design to obtain a holistic view of the entire DFG and continuously self-adaptively optimizes the scheduling process. Furthermore, a complete workflow is implemented, supporting making refinements to the software DFG mapping results. DFGAS represents a scheduling scheme of CGRA that is worth exploring, achieving hardware-software co-design that balances energy efficiency and flexibility. Experiments show that DFGAS achieves 1.35 × energy efficiency improvement over a dataflow-driven CGRA and 1.9 × energy efficiency improvement over a state-of-the-art pure static CGRA.

TL;DR: A new version of SimpleScalar that has been adapted to the ARM instruction set is used to characterize the performance of the benchmarks using configurations similar to current and next generation embedded processors.

TL;DR: The parallel landscape is frame with seven questions, and the following are recommended to explore the design space rapidly: • The overarching goal should be to make it easy to write programs that execute efficiently on highly parallel computing systems • The target should be 1000s of cores per chip, as these chips are built from processing elements that are the most efficient in MIPS (Million Instructions per Second) per watt, MIPS per area of silicon, and MIPS each development dollar.

TL;DR: Results show that high performance can be obtained in each of the three modes--ILP, TLP, and DLP-demonstrating the viability of the polymorphous coarse-grained approach for future microprocessors.

TL;DR: The Tera-op reliable intelligently adaptive processing system (TRIPS) architecture seeks to deliver system-level configurability to applications and runtime systems by employing the concept of polymorphism.