Patent
A stack arrangement
Cheryl Sharmani Selvanagam,Ranjan Rajoo,Xiaowu Zhang +2 more
- 12 Feb 2010
TL;DR: In this article, a stack arrangement is provided in which includes a semiconductor arrangement, a substrate, a via formed through the substrate, and a conductive portion arranged in the via.
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Abstract: In an embodiment, a stack arrangement is provided. The stack arrangement may include a semiconductor arrangement, the semiconductor arrangement including a substrate; a via formed through the substrate; and a conductive portion arranged in the via. The stack arrangement may further include an interconnect portion arranged over the via; a bond pad portion arranged between the semiconductor arrangement and the interconnect portion, the bond pad portion may include a bond pad circumferential portion arranged at least partially circumferential with respect to the via and at a first distance away from the conductive portion; and at least one bond pad electrical connection extending from within the bond pad circumferential portion to the conductive portion; wherein the interconnect portion may be arranged away from the conductive portion via the bond pad portion.
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References
Patent
Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
Kyle K. Kirby,Warren M. Farnworth +1 more
- 17 Apr 2006
TL;DR: In this paper, the authors proposed a method of forming a multiconductor via extending through a plurality of stacked dice that includes the conductive elements and dielectric material, and then depositing metal upon the regions.
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Patent
Integrated circuit with improved interconnect structure and process for making same
Min-Chih John Hsuan
- 11 Jun 2002
TL;DR: A semiconductor die and an associated low-resistance interconnect located primarily on the bottom surface of such die is disclosed in this paper, providing a flexible packaging structure permitting easy interconnected with other integrated circuits; in this manner, a number of such circuits can be stacked to create high circuit density multi-chip modules.
80
Patent
Die stacking recessed pad wafer design
Richard P. Rangel
- 09 Jun 2005
TL;DR: In this paper, a die-to-die alignment structure is proposed that facilitates the alignment and/or positional retention of die during a 3-D stacked assembly process, and a die to die alignment structure for 3D stacked assemblies is described.
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