Proceedings Article10.1145/1278480.1278537
A self-tuning configurable cache
Ann Gordon-Ross,Frank Vahid +1 more
- 04 Jun 2007
- pp 234-237
TL;DR: A self-tuning cache is introduced that performs transparent runtime cache tuning, thus relieving the application designer and/or compiler from predetermining an application's cache configuration.
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Abstract: The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can reduce memory subsystem energy by 62% on average. We introduce a self-tuning cache that performs transparent runtime cache tuning, thus relieving the application designer and/or compiler from predetermining an application's cache configuration. The self-tuning cache applies tuning at a determined tuning interval. A good interval balances tuning process energy overhead against the energy overhead of running in a sub-optimal cache configuration, which we show wastes much energy. We present a self-tuning cache that dynamically varies the tuning interval, resulting in average energy reduction of as much as 29%, falling within 13% of an oracle-based optimal method.
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Citations
System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems
Weixun Wang,Prabhat Mishra +1 more
TL;DR: This paper efficiently integrate DVS and DCR techniques together to make decisions judiciously so that the total energy consumption is minimized and shows that this approach outperforms existing leakage-aware DVS techniques by 47.6% and leakage-oblivious DVS + DCR technique by up to 23.5%.
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Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems
Weixun Wang,Prabhat Mishra +1 more
- 03 Jan 2010
TL;DR: This paper efficiently integrate processor voltage scaling and cache reconfiguration together that is aware of leakage power to minimize overall system energy consumption and outperforms existing techniques by on average 12 - 23%.
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A survey on cache tuning from a power/energy perspective
Wei Zang,Ann Gordon-Ross +1 more
TL;DR: This survey focuses on state-of-the-art offline static and online dynamic cache tuning techniques and summarizes the techniques' attributes, major challenges, and potential research trends to inspire novel ideas and future research avenues.
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Smart cache: A self adaptive cache architecture for energy efficiency
Karthik T. Sundararajan,Timothy M. Jones,Nigel Topham +2 more
- 18 Jul 2011
TL;DR: A decision tree based machine learning model is developed to control the adaptation and automatically reconfigure the cache to the best configuration and the energy-delay of the Smart cache is on average 14% better than state-of-the-art cache reconfiguration architectures.
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
Chenjie Yu,Peter Petrov +1 more
- 13 Jun 2010
TL;DR: This work takes a different approach in which tasks' memory bandwidth requirements are taken into account when identifying a cache partitioning for multi-programmed and/or multithreaded workloads, in which the overall system bandwidth requirement is minimized for the target workload.
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