A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists
Paul Tafertshofer,Andreas Ganz,Manfred Henftling +2 more
- 13 Nov 1997
- pp 648-655
TL;DR: A flexible and efficient approach to evaluating implications as well as deriving indirect implications in logic circuits based on a graph model of a circuit's clause description called implication graph which combines both the flexibility of SAT-based techniques and high efficiency of structure based methods.
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Abstract: The paper presents a flexible and efficient approach to evaluating implications as well as deriving indirect implications in logic circuits. Evaluation and derivation of implications are essential in ATPG, equivalence checking, and netlist optimization. Contrary to other methods, the approach is based on a graph model of a circuit's clause description called implication graph. It combines both the flexibility of SAT-based techniques and high efficiency of structure based methods. As the proposed algorithms operate only on the implication graph, they are independent of the chosen logic. Evaluation of implications and computation of indirect implications are performed by simple and efficient graph algorithms. Experimental results for various applications relying on implication demonstrate the effectiveness of the approach.
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Citations
Fault diagnosis and logic debugging using Boolean satisfiability
TL;DR: This work proposes a novel Boolean satisfiability-based method for multiple-fault diagnosis and multiple-design-error diagnosis in combinational and sequential circuits and suggests that satisfiability captures significant characteristics of the problem of diagnosis.
292
Boolean satisfiability in electronic design automation
Joao Marques-Silva,Karem A. Sakallah +1 more
- 01 Jun 2000
TL;DR: This tutorial paper is aimed at introducing the EDA professional to the Boolean satisfiability problem, and highlights the use of SAT models to formulate a number of EDA problems in such diverse areas as test pattern generation, circuit delay computation, logic optimization, combinational equivalence checking, bounded model checking and functional test vector generation.
Fault diagnosis and logic debugging using Boolean satisfiability
Andreas Veneris
- 29 May 2003
TL;DR: This work proposes a model-free satisfiability-based solution to Fault diagnosis and logic debugging for digital VLSI design problems and shows that satisfiability captures significant problem characteristics and it offers different trade-offs.
Checking Equivalence for Partial Implementations.
Christoph Scholl,Bernd Becker +1 more
- 01 Jan 2001
TL;DR: This work considers the problem of checking whether a partial implementation can (still) be extended to a complete design which is equivalent to a given full specification, and presents several algorithms trading off accuracy and computational resources.
85
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João P. Marques Silva,Karem A. Sakallah +1 more
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Improved deterministic test pattern generation with applications to redundancy identification
M.H. Schulz,E. Auth +1 more
TL;DR: The authors present an improved implication procedure and an improved unique sensitization procedure that is capable of both successfully generating a test pattern for all testable faults in a set of combinational benchmark circuits, and of identifying all redundant faults with less than ten backtrackings.
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TL;DR: This paper presents logic optimization techniques for multilevel combinational networks which apply a sequence of perturbations which result in simplification of the circuit through wires/gates addition and removal which are guided by the ATPG based reasoning.
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