A Rule-Based System for Optimizing Combinational Logic

TL;DR: Theoretical Reasoning in Design: Design by Generation, a guide to designing for the 21st Century with real-time constraints.

TL;DR: SOCRATES optimizes logic using boolean and algebraic minimization techniques, and it optimizes circuits derived from this logic in a user defined technology with a rule based expert system.

Abstract: A system and method for selectively simulating logic circuit designs in which a data tables generator receives information from a schematic entry program or netlist entry file and produces data tables for use by a simulator. A designer provides inputs to the data tables generator from a schematic entry program or a netlist entry file. The data tables generator generates from the information received a table of used integrated circuits and a table of their connections. A simulator then receives the output from the data tables generator and produces a design simulation program table that executes integrated circuit model subroutine stored in an integrated circuit model reference library and netlist subroutines stored in a netlist connectivity table. The system may also be used for testing logic circuits on a printed circuit board by capturing signals from a potentially defective logic section of the printed circuit board and feeding them into test points of the integrated circuit simulated by the computer simulator.

TL;DR: This paper introduces a new approach to performance-driven template mapping for high-level synthesis that focuses on datapath-intensive ASIC design, though the concepts are also highly applicable to compiler development.

TL;DR: R1 is a program that configures VAX-11/780 computer systems and uses Match as its principal problem solving method; it has sufficient knowledge of the configuration domain and of the peculiarities of the various configuration constraints that at each step in the configuration process, it simply recognizes what to do.

TL;DR: The evolution of the Logic Synthesis System is described from an experimental tool to a production system for the synthesis of masterslice chip implementations and the primary reasons for this success are the use of local transformations to simplify logic representations at several levels of abstraction.

TL;DR: The Design Automation Assistant speeds VLSI chip design and makes explicit some of the intuition and common sense that are important elements of expertise.