Journal Article10.1109/TC.1984.1676353
A Robust Matrix-Multiplication Array
Varman,Ramakrishnan,Fussell +2 more
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TL;DR: This correspondence presents a robust VLSI array processor for matrix multiplication that is driven by a host computer as a peripheral and the I/O bandwidth required to drive the array is a constant, independent of the problem size.
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Abstract: Matrix multiplication algorithms have been proposed for VLSI array processors. Random defects in the silicon wafer and fabrication errors render processors and data paths in the array faulty, and may cause the algorithm to fail despite a significant number of nonfaulty processors. This correspondence presents a robust VLSI array processor for matrix multiplication. The array is driven by a host computer as a peripheral and the I/O bandwidth required to drive the array is a constant, independent of the problem size. Multiplication of two n x n matrices requires O(n) processors and has a time complexity of O(n2) cydes.
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Citations
A Bibliography of IEEE Transactions on Computers (1980{1989)
Nelson H. F. Beebe
- 01 Jan 2012
TL;DR: (2m± 1) [HGS83b].
On Mapping Cube Graphs onto VLSI Arrays
I. V. Ramakrishnan
- 13 Dec 1984
TL;DR: Formal models of linear, mesh and hexagonal arrays are presented that are well-suited for VLSI (very large scale integration) and a model of a logical linear array, wherein adjacent processors may be separated by wires of arbitrary length is presented.
6
On Matrix Multiplication Using Array Processors
Peter Varman,I. V. Ramakrishnan +1 more
- 15 Jul 1985
TL;DR: This paper presents a new approach to solving the problem of how to multiply two n×n matrices on a one-dimensional array processor with respect to Ω(n2) time complexity.
5
A gracefully degradable VLSI system for linear programming
TL;DR: The use of a fault-tolerant VLSI system for storing and solving linear programming problems is presented and it is shown that the total silicon area required by this structure is only a constant factor higher than that of a complete binary tree.
4
Inner-product based signal processing: Algorithms and VLSI implementation
Chiung-Hsing Chen
- 01 Jan 1994
TL;DR: This dissertation is particularly dedicated to parents for their love and support during seven years studying at Ohio University and to MOSIS program for the supporting fabrication of the chip.
3
References
Why systolic architectures
TL;DR: The basic principle of systolic architectures is reviewed and it is explained why they should result in cost-effective, highperformance special-purpose systems for a wide range of problems.
Systolic Arrays for (VLSI).
Hsiang-Tsung Kung,Charles E. Leiserson +1 more
- 01 Dec 1978
TL;DR: A systolic system is a network of processors which rhythmically compute and pass data through the system, and almost all processors used in the networks are identical, so that a regular flow of data is kept up in the network.
978
Design of a Massively Parallel Processor
TL;DR: The massively parallel processor (MPP) as discussed by the authors was designed to process satellite imagery at high rates, achieving 8-bit integer data, addition can occur at 6553 million operations per second (MOPS) and multiplication at 1861 MOPS.
831
Hamilton Paths in Grid Graphs
TL;DR: This work gives necessary and sufficient conditions for the graph to have a Hamilton path between these two nodes, and provides a new, relatively simple, proof of the result that the Euclidean traveling salesman problem is NP-complete.