Proceedings Article10.1145/996566.996688
A robust algorithm for approximate compatible observability don't care (CODC) computation
Nikhil Saluja,Sunil P. Khatri +1 more
- 07 Jun 2004
- pp 422-427
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TL;DR: This paper presents an algorithm to compute approximate CODCs (ACODCs), an approximation of its CODC, and proves the soundness of the approach, and performs extensive experiments to explore the trade-off between memory utilization, speed and accuracy.
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Abstract: Compatible Observability Don't Cares (CODCs) are a powerful means to express the flexibility present at a node in a multi-level logic network. Despite their elegance, the applicability of CODCs has been hampered by their computational complexity. The CODC computation for a network involves several image computations, which require the construction of global BDDs of the circuit nodes. The size of BDDs of circuit nodes is unpredictable, and as a result, the CODC computation is not robust. In practice, CODCs cannot be computed for large circuits due to this limitation.In this paper, we present an algorithm to compute approximate CODCs (ACODCs). This algorithm allows us to compute compatible don't cares for significantly larger designs. Our ACODC algorithm is scalable in the sense that the user may trade off time and memory against the accuracy of the ACODCs computed. The ACODC is computed by considering a subnetwork rooted at the node of interest, up to a certain topological depth, and performing its don't care computation. We prove that the ACODC is an approximation of its CODC.We have proved the soundness of the approach, and performed extensive experiments to explore the trade-off between memory utilization, speed and accuracy. We show that even for small topological depths, the ACODC computation gives very good results. Our experiments demonstrate that our algorithm can compute ACODCs for circuits whose CODC computation has not been demonstrated to date. Also, for a set of benchmark circuits whose CODC computation yields an average 28% reduction in literals after optimization, our ACODC computation yields an average 22% literal reduction. Our algorithm has runtimes which are about 25x and memory utilization which is 33x better that of the CODC computation of SIS.
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Citations
Scalable don't-care-based logic optimization and resynthesis
TL;DR: The proposed resynthesis is capable of substantial logic restructuring, is customizable to solve a variety of optimization tasks, and has reasonable runtime on industrial designs.
106
SAT sweeping with local observability don't-cares
Qi Zhu,Nathan Kitchen,Andreas Kuehlmann,Alberto Sangiovanni-Vincentelli +3 more
- 24 Jul 2006
TL;DR: This paper uses a novel technique to bound the use of ODCs and thus the computational effort to find them, while still finding a large fraction of them, and demonstrates that ODC-based SAT sweeping results in significantly more graph simplification with great benefit for Boolean reasoning with a moderate increase in computational effort.
SAT-Based Complete Don't-Care Computation for Network Optimization
Alan Mishchenko,Robert K. Brayton +1 more
- 07 Mar 2005
TL;DR: SAT reduces the runtime and enhances robustness, making don't-cares affordable for a variety of other Boolean methods applied to the network, and gives a SAT-basedDon't-care computation algorithm that is more efficient than BDD-based algorithms.
Parallelizing CAD: a timely research agenda for EDA
Bryan Catanzaro,Kurt Keutzer,Bor-Yiing Su +2 more
- 08 Jun 2008
TL;DR: This work proposes that a key area of CAD research is to identify the design patterns underlying CAD applications and then build CAD application frameworks that aid efficient parallel software implementations of these design patterns.
Node Mergers in the Presence of Don't Cares
Stephen M. Plaza,Kai-Hui Chang,Igor L. Markov,Valeria Bertacco +3 more
- 23 Jan 2007
TL;DR: An ODC-based node merging algorithm that performs efficient global ODC analysis (considering the entire netlist) through simulation and SAT and operates on arbitrarily mapped netlists, allowing for powerful post-synthesis optimizations.
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Sharad Malik,Angie Wang,Robert K. Brayton,Alberto Sangiovanni-Vincentelli +3 more
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TL;DR: The results of a formal logic verification system implemented as part of the multilevel logic synthesis system MIS are discussed and it has been possible to carry out formal verification for a larger set of networks than with existing verification systems.
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Soha Hassoun,Tsutomu Sasao +1 more
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TL;DR: Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification that presents key developments, outlines future challenges, and lists essential references.
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