Proceedings Article10.1109/ICSICT.2010.5667886
A research of dual-port SRAM cell using 8T
Kai-ji Zhang,Kun Chen,Pan Weitao,Pei-Jun Ma +3 more
- 13 Dec 2010
- pp 2040-2042
TL;DR: This paper presents a 6T- SRAM (1WR) and two types of 8T-SRAM cell (2WR 1W1R), and compares the SNM sensitivity and the write/read operations time of 1WR 1 W1R cell.
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Abstract: High speed, low power and compatibility with standard technology Static random access memory (SRAM) is essential for system on chip (SoC) technology. In this paper, we first present a 6T-SRAM (1WR) and two types of 8T-SRAM cell(2WR 1W1R). After that how the (1W1R) cell work with external unit is explained, and we compare the SNM sensitivity and the write/read operations time of 1WR 1W1R cell.
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Citations
A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology
Jitendra Kumar Mishra,Harshit Srivastava,Prasanna Kumar Misra,Manish Goswami +3 more
- 01 Dec 2018
TL;DR: The proposed 11T SRAM cell for improving read stability and reducing the static power dissipation is proposed in this work and has been verified in 40nm CMOS technology node using cadence virtuoso tool.
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A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures
TL;DR: A 512-kbit 2P SRAM macro using 28-nm high-K/metal gate bulk CMOS technology has been designed, confirming experimentally that the worst minimum operation voltage can be reproduced by the test circuit.
8
Patent
Method and apparatus for read assist to compensate for weak bit
Jonathan Chang,Cheng Hung Lee,Chung-Cheng Chou,Hung-jen Liao,Bin-Hau Lo +4 more
- 02 Apr 2012
TL;DR: In this paper, a memory assist apparatus includes a detection circuit and a compensation circuit, which are configured to detect whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold.
6
Analytical distinction between cntfet based and mosfet based srams and logic gates
Turja Nandy,Arin Dutta,Zahid Mahmood +2 more
- 01 Jan 2015
TL;DR: In this paper, the authors compare the distinct properties of Carbon Nanotube Field Effect Transistor (CNTFET) based applications with MOSFET based applications in memory and digital electronics technology.
References
Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access
Koji Nii,Yasumasa Tsukamoto,Makoto Yabuuchi,Y. Masuda,S. Imaoka,K. Usui,Shigeki Ohbayashi,Hiroshi Makino,Hirofumi Shinohara +8 more
TL;DR: An access scheme for a synchronous dual- port (DP) SRAM that minimizes the 8T-DP-cell area and maintains cell stability is proposed and a priority row decoder circuit and shifted bit- line access scheme eliminates access conflict issues.
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