A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test
Hratch Mangassarian,Andreas Veneris,Sean Safarpour,Marco Benedetti,Duncan Smith +4 more
- 05 Nov 2007
- pp 240-245
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TL;DR: This work proposes a performance-driven, succinct and parametrizable quantified Boolean formula (QBF) satisfiability encoding and its hardware implementation for modeling sequential circuit behavior.
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Abstract: Many CAD for VLSI techniques use time-frame expansion, also known as the iterative logic array representation, to model the sequential behavior of a system Replicating industrial-size designs for many time-frames may impose impractically excessive memory requirements This work proposes a performance-driven, succinct and parametrizable quantified Boolean formula (QBF) satisfiability encoding and its hardware implementation for modeling sequential circuit behavior This encoding is then applied to three notable CAD problems, namely bounded model checking (BMC), sequential test generation and design debugging Extensive experiments on industrial circuits confirm outstanding run-time and memory gains compared to state-of-the-art techniques, promoting the use of QBF in CAD for VLSI
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Citations
•Journal Article
sKizzo : A suite to evaluate and certify QBFs
TL;DR: SKizzo as mentioned in this paper is a system designed to evaluate and certify QBFs by means of propositional skolemization and symbolic reasoning, and it can be used to verify QBFs.
137
Automated Design Debugging With Maximum Satisfiability
TL;DR: This paper presents a novel formulation of the debugging problem using MaxSAT to improve the performance and applicability of automated debuggers, and introduces two performance improvements to further reduce the time required to find all error sources within the design by an order of magnitude.
A uniform approach for generating proofs and strategies for both true and false QBF formulas
Alexandra Goultiaeva,Allen Van Gelder,Fahiem Bacchus +2 more
- 16 Jul 2011
TL;DR: This paper demonstrates that a circuitbased QBF solver can be exploited to obtain a QResolution proof of the truth or the falsity of a QBF, and shows that the proof is a representation of the winning strategy.
A Microeconomic Model for Hierarchical Bandwidth Sharing in Dynamic Spectrum Access Networks
Dusit Niyato,Ekram Hossain +1 more
TL;DR: The problem of hierarchical bandwidth sharing in dynamic spectrum access (or cognitive radio) environment is considered as an interrelated market model used in microeconomics for which a multiple-level market is established among the primary, secondary, tertiary, and quaternary services.
61
Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test
TL;DR: This work proposes a succinct QBF encoding for modeling sequential circuit behavior, which shows memory reductions in the order of 90 percent and demonstrate competitive runtimes compared to state-of-the-art SAT techniques.
References
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Matthew W. Moskewicz,Conor F. Madigan,Ying Zhao,Lintao Zhang,Sharad Malik +4 more
- 22 Jun 2001
TL;DR: The development of a new complete solver, Chaff, is described which achieves significant performance gains through careful engineering of all aspects of the search-especially a particularly efficient implementation of Boolean constraint propagation (BCP) and a novel low overhead decision strategy.
An Extensible SAT-solver
Niklas Een,Niklas Sörensson +1 more
- 05 May 2003
TL;DR: This article presents a small, complete, and efficient SAT-solver in the style of conflict-driven learning, as exemplified by Chaff, and includes among other things a mechanism for adding arbitrary boolean constraints.
Bounded Model Checking
TL;DR: This article surveys a technique called Bounded Model Checking (BMC), which uses a propositional SAT solver rather than BDD manipulation techniques, and is widely perceived as a complementary technique to BDD-based model checking.
Fault diagnosis and logic debugging using Boolean satisfiability
TL;DR: This work proposes a novel Boolean satisfiability-based method for multiple-fault diagnosis and multiple-design-error diagnosis in combinational and sequential circuits and suggests that satisfiability captures significant characteristics of the problem of diagnosis.
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Conflict driven learning in a quantified Boolean satisfiability solver
Lintao Zhang,Sharad Malik +1 more
- 10 Nov 2002
TL;DR: It is proved that under certain conditions, tautology clauses obtained from resolution in QBF also obey the rules for implication and conflicts of regular (non-tautology) clauses; and therefore they can be treated as regular clauses and used in future search.
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