Open Access
A parallel rendering algorithm for mimd architectures
Thomas W. Crockett,Tobias Orloff +1 more
- 01 Jun 1991
16
TL;DR: A rendering algorithm targeted to distributed memory MIMD architectures that exploits both object-level and pixel-level parallelism for maximum performance and is found to be limited primarily by communication overheads.
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Abstract: Applications such as animation and scientific visualization demand high performance rendering of complex three dimensional scenes. To deliver the necessary rendering rates, highly parallel hardware architectures are required. The challenge is then to design algorithms and software which effectively use the hardware parallelism. This paper describes a rendering algorithm targeted to distributed memory MIMD architectures. For maximum performance, the algorithm exploits both object-level and pixel-level parallelism. The behavior of the algorithm is examined both analytically and experimentally. Its performance for large numbers of processors is found to be limited primarily by communication overheads. An experimental implementation for the Intel iPSC/860 shows increasing performance from 1 to 128 processors across a wide range of scene complexities. It is shown that minimal modifications to the algorithm will adapt it for use on shared memory architectures as well.
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Citations
A sorting classification of parallel rendering
TL;DR: A classification scheme is described that is based on where the sort from object coordinates to screen coordinates occurs, which it is believed is fundamental whenever both geometry processing and rasterization are performed in parallel.
A sorting classification of parallel rendering
Steven Molnar,Michael Cox,David S. Ellsworth,Henry Fuchs +3 more
- 10 Dec 2008
TL;DR: In this article, the authors describe a classification scheme that provides a more structured framework for reasoning about parallel rendering, based on where the sort from object coordinates to screen coordinates occurs, which is fundamental whenever both geometry processing and rasterization are performed in parallel.
456
Parallelized direct execution simulation of message-passing parallel programs
TL;DR: This paper describes methods suitable for parallelized direct execution simulation of message-passing parallel programs, and reports on the performance of such a system, LAPSE (Large Application Parallel Simulation Environment), which has built on the Intel Paragon.
A MIMD rendering algorithm for distributed memory architectures
Thomas W. Crockett,Tobias Orloff +1 more
- 01 Nov 1993
TL;DR: A parallel rendering algorithm targeted to MIMD distributed-memory message-passing architectures that exploits both object-level and image level parallelism and Scalability to large numbers of processors is found to be limited primarily by communication overheads.
40
Design considerations for parallel graphics libraries
Thomas W. Crockett
- 01 Jun 1994
TL;DR: This paper provides a tutorial introduction to some of the issues which arise in designing parallel graphics libraries and their underlying rendering algorithms, with a focus on polygon rendering for distributed memory message-passing systems.
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TL;DR: The architecture and initial algorithms for Pixel-Planes 5, a heterogeneous multi-computer designed both for high-speed polygon and sphere rendering and for supporting algorithm and application research in interactive 3D graphics are introduced.
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A parallel processor architecture for graphics arithmetic operations
John G. Torborg
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TL;DR: A graphics processor architecture which can be configured with an arbitrary number of identical processors operating in parallel, substantially simplifying software development and allowing complex rendering functions to take advantage of the multiple processors.
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Communication overhead on the Intel iPSC-860 hypercube
Shahid H. Bokhari
- 01 May 1990
TL;DR: The results of experiments carried out on the recently introduced Intel iPSC-860 hypercube permit the following major conclusions to be made about this machine: Contrary to popular belief, the time required to communicate between nodes does depend on the number of intervening hops on both machines.
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