Journal Article10.1145/964965.808580
A parallel processor system for three-dimensional color graphics
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TL;DR: The hardware architecture and the employed algorithm of a parallel processor system for three-dimensional color graphics to generate realistic color graphics is described.
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Abstract: This paper describes the hardware architecture and the employed algorithm of a parallel processor system for three-dimensional color graphics. The design goal of the system is to generate realistic...
read more
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Citations
A parallel processor architecture for graphics arithmetic operations
John G. Torborg
- 01 Aug 1987
TL;DR: A graphics processor architecture which can be configured with an arbitrary number of identical processors operating in parallel, substantially simplifying software development and allowing complex rendering functions to take advantage of the multiple processors.
79
Subanosecond pixel rendering with million transistor chips
Nader Gharachorloo,Satish Gupta,Erden Hokenek,Peruvemba S. Balasubramanian,Bill Bogholtz,Christian Mathieu,Christos Stamoulis Zoulas +6 more
- 01 Jun 1988
TL;DR: The design of a VLSI chip and a graphics system that can sustain sub-nanosecond pixel rendering rates for three-dimensional polygons and can be used to render about a million Z-Buffered and Gourard shaded polygons per second is presented.
50
Fast image generation of construcitve solid geometry using a cellular array processor
Hiroyuki Sato,Ishii Mitsuo,Keiji Sato,Morio Ikesaka,Hiroaki Ishihata,Masanori Kakimoto,Katsuhiko Hirota,Inoue Kouichi +7 more
- 01 Jul 1985
TL;DR: A general CSG hidden surface algorithm is adopted that enables display of both Boundary representation and Constructive Solid Geometry and it is proposed that this technique subdivides the model into submodels by dividing the CSG tree at union nodes.
47
A scalable hardware render accelerator using a modified scanline algorithm
Michael W. Kelley,Stephanie Winner,Kirk B. Gould +2 more
- 01 Jul 1992
TL;DR: A hardware accelerator for 3D ren&ring, based on a mcdifkd scanline algorithm, is presented, which has a very high performance/cost ratio, but maintains a low entry cost and a high degree of scalability — key issues for incorporation in personal computers.
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TL;DR: This paper proposes an alternative to several special-purpose parallel architectures suggested, which aims at speeding up scan conversion by providing a simple and scalable architecture for parallel processing of scan conversion data.
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