A New Approach for Multi-Valued Computing Using Machine Learning

TL;DR: The approach, given a MVL function, performs iterative linear regressions on all input and output combinations to derive a set of linear expressions, which are hardware implementation friendly and can be implemented with simple gates and summation functions.

Abstract: To continue scaling in future and to meet emerging application requirements, revolutionary concepts are required not just on "how can we find better switches to implement computers", but also on "how computers compute logic". Multi-Valued Logic (MVL) provides one such opportunity, since efficient implementation of MVL can allow compact and enhanced information processing and be orders of magnitude efficient than binary CMOS. Emerging devices such as Quantum Dots, Magnetic Tunnel Junctions (MTJs), Carbon Nanotube FETs (CNTFETs), Spin Wave Devices etc., provide an avenue for hardware implementation of MVL. So far, MVL lagged behind CMOS due to (a) complexities associated with traditional logic decomposition approaches, which result in many MVL minterms, complex polynomials of order greater than two, and cumbersome decision diagrams that are difficult to implement, and (b) multi-valued data representation, processing and communication using binary switches and medium, which are inefficient. In this paper, we propose a transformative new direction for multi-valued logic decomposition (problem (a)) utilizing concepts from machine learning and nanoelectronics. In our approach, given a MVL function, we perform iterative linear regressions on all input and output combinations to derive a set of linear expressions. A visual pattern matching technique is then applied to derive selection conditions for each linear expression based on the function inputs. The set of linear expressions and corresponding selection criteria ensure that for all function inputs, correct outputs are obtained. The resulting linear expressions are hardware implementation friendly and can be implemented with simple gates and summation functions. In this paper, we show an approach to solve (b) by implementing a quaternary multiplier using our technique. Our detailed comparison with existing methods suggests huge benefits can be attained with the proposed method.