Open AccessProceedings Article10.1109/ESSCIRC.2011.6044993

A monolithically-integrated optical receiver in standard 45-nm SOI

- 13 Oct 2011

- pp 407-410

TL;DR: This work demonstrates that photonics and electronics can be jointly integrated in a standard 45-nm SOI process and is shown to operate with μA-sensitivity at 3.5 Gb/s.

Abstract: A monolithically-integrated optical receiver for low-energy on-chip and off-chip communication is presented. The monolithic photodiode integration enables the energy-efficient and high-sensitivity sense-amplifier-based receiver design. The receiver is characterized in situ and shown to operate with μA-sensitivity at 3.5 Gb/s with a power consumption of 180 μW (52 fJ/bit) and area of 108 μm2. This work demonstrates that photonics and electronics can be jointly integrated in a standard 45-nm SOI process.

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A monolithically-integrated optical receiver for lowenergy on-chip and off-chip communication is presented.. This work demonstrates that photonics and electronics can be jointly integrated in a standard 45-nm SOI process.

Fig. 5. The measurement shows the receiver’s ability to distinguish between a DC optical-1 and optical-0.

Fig. 1. An example optical link with chip-to-chip and intra-chip communication links shown. A CW laser source is coupled onto Chip A through a vertical grating. Two ring-resonant modulators imprint data onto two wavelength-channels, λ0 and λ1, which propagate along the waveguide. The bus is routed over an optical fiber to Chip B. The drop rings on Chip B are each tuned to either λ0 and λ1 to select that channel from the bus and direct it to the correct data receiver. A second set of wavelengths, λ2 and λ3 carry data from Chip B to Chip A.

Fig. 2. Optical data receiver architecture. The LSA (a) is followed by an output buffer stage (d) and dynamic-to-static converter (e), before being fed into the digital backend infrastructre (f). The chip has receivers connected to integrated PDs (g) or electrical diode-emulation circuits (h). The simulation model is shown in (i). A cross-section of the implemented PD and optical mode is shown in (j).

Fig. 8. Die, backside photonic cell and receiver photos.

Citations

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References

Proceedings Article•10.1109/ISSCC.2009.4977511

Optical I/O technology for tera-scale computing

Young, +6 more

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TL;DR: Results are described for both near and long-term chip-to-chip optical interconnect architectures that replace electrical interconnect between chips with its terahertz bandwidth, low loss, and low cross-talk.

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Optical I/O technology for tera-scale computing

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TL;DR: In this paper, the authors describe both a near term and a long term optical interconnect solution, the first based on a packaging architecture and the second based on monolithic photonic CMOS architecture, which enables higher bandwidth and lower energy per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) detectors.

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Circuits and techniques for high-resolution measurement of on-chip power supply noise

Elad Alon, +2 more

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TL;DR: This paper presents a technique for characterizing the statistical properties and spectrum of power supply noise using only two on-chip low-throughput samplers that utilize a voltage-controlled oscillator to perform high-resolution analog-to-digital conversion with minimal hardware.

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A low-power 20-GHz 52-dB/spl Omega/ transimpedance amplifier in 80-nm CMOS

C. Kromer, +6 more

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- IEEE Journal of Solid-state Circuits

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Addressing link-level design tradeoffs for integrated photonic interconnects

Michael Georgas, +4 more

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TL;DR: A set of link component models for performing interconnect design-space exploration connected to the underlying device and circuit technology is presented, demonstrating the link-level interactions between components in achieving the optimal degree of parallelism and energy-efficiency.

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A monolithically-integrated optical receiver in standard 45-nm SOI

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1. What are the contributions in "A monolithically-integrated optical receiver in standard 45-nm soi" ?

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Citations

DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling

A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning

Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS

10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS

A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS

References

Optical I/O technology for tera-scale computing

Optical I/O technology for tera-scale computing

Circuits and techniques for high-resolution measurement of on-chip power supply noise

A low-power 20-GHz 52-dB/spl Omega/ transimpedance amplifier in 80-nm CMOS

Addressing link-level design tradeoffs for integrated photonic interconnects

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