Proceedings Article10.1109/HICSS.2006.15
A Methodology for Generating Application-Specific Heterogeneous Processor Arrays
Stephen Craven,Cameron D. Patterson,Peter Athanas +2 more
- 04 Jan 2006
- Vol. 10, pp 251
TL;DR: A design methodology is proposed targeting signal processing applications that maps a parallelized C program onto a homogenous array of processors linked by simple point-to-point connections, which increases the performance of the array, while the common basic interface between processors eases optimization, implementation, debugging, and verification.
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Abstract: Hardware designers are increasingly turning to Single Chip Multi-Processors to achieve power and throughput goals To further increase performance for a specific application the chips array of processors can be tailored to their program, creating an application-specific multiprocessor While much Hardware/Software Codesign research has been conducted on optimizing heterogeneous processing arrays, shortcomings exist in design scalability, simulation, verification, rapid prototyping, and the requirement of specialized skill sets To address these deficiencies, a design methodology is proposed targeting signal processing applications that maps a parallelized C program onto a homogenous array of processors linked by simple point-to-point connections By individually optimizing each processor for its specific program the performance of the array is increased, while the common basic interface between processors eases optimization, implementation, debugging, and verification
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Citations
Application Specific Customization and Scalability of Soft Multiprocessors
Deepak Unnikrishnan,Jia Zhao,Russell Tessier +2 more
- 05 Apr 2009
TL;DR: An automated parallel compilation environment for multiple soft processors which incorporates parallel compilation and inter-processorcommunication structures is described and it is shown that the new automated infrastructure allows for an evaluation of area, performance, and power tradeoffs for a range of architectural choices.
Patent
Designing an ASIC Based on Execution of a Software Program on a Processing System
Tommy K. Eng
- 22 May 2007
TL;DR: In this article, a software program may be stored which includes program instructions which implement a function and the software program can be executed on a processing system at a desired system speed and may be validated based on the execution.
13
Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach
TL;DR: This paper presents the parallelization and the embedding of a real time image stabilization algorithm on a SoPC platform and presents both software and hardware implementation with performance results on a Xilinx SoPC target.
12
A C++-embedded Domain-Specific Language for programming the MORA soft processor array
Wim Vanderbauwhede,Martin Margala,Sai Rahul Chalamalasetti,Sohan Purohit +3 more
- 07 Jul 2010
TL;DR: A Domain-Specific Language (DSL) for high-level programming of the MORA soft processor array, embedded in C++, providing designers with a familiar language framework and the ability to compile designs using a standard compiler for functional testing before generating the FPGA bitstream using the MorA toolchain.
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs
Xiaofang Wang,Pallav Gupta +1 more
TL;DR: This article presents an application-specific design methodology for multiprocessor-on-programmable-chip architectures that target applications involving large matrices and floating-point operations and aims to customize the architecture to match the diverse computation and communication requirements of the application tasks.
3
References
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Michael Taylor,Jung Hun Kim,Jason Miller,David Wentzlaff,Fae Ghodrat,Ben Greenwald,Henry Hoffman,Paul Johnson,Jae-Wook Lee,Woo Sik Lee,A. Ma,Arvind Saraf,M. Seneski,Nathan Shnidman,Volker Strumpen,Matthew I. Frank,Saman Amarasinghe,Anant Agarwal +17 more
TL;DR: The Raw microprocessor research prototype uses a scalable instruction set architecture to attack the emerging wire-delay problem by providing a parallel, software interface to the gate, wire and pin resources of the chip.
Power efficient processor architecture and the cell processor
Harm Peter Hofstee
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TL;DR: In this paper, the authors provide a background and rationale for some of the architecture and design decisions in the cell processor, a processor optimized for compute-intensive and broadband rich media applications, jointly developed by Sony Group, Toshiba, and IBM.
The Stanford Hydra CMP
TL;DR: The design of a CMP is motivated, the architecture of the Hydra design is described with a focus on its speculative thread support, and the prototype implementation is described.
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning
Roman Lysecky,Frank Vahid +1 more
- 07 Mar 2005
TL;DR: W warp processing is proposed, a technique capable of optimizing a software application by dynamically and transparently re-implementing critical software kernels as custom circuits in on-chip configurable logic, and it is demonstrated that the soft-core based warp processor achieves average speedups of 5.8 and energy reductions of 57% compared to the soft core alone.
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