Proceedings Article10.1109/ISCAS.2005.1464767
A memory-reduced log-MAP kernel for turbo decoder
Tsung-Han Tsai,Cheng-Hung Lin,An-Yeu Wu +2 more
- 23 May 2005
- pp 1032-1035
TL;DR: The comparison result shows the proposed architecture can reduce the memory size to 26% of the classical architecture, and the memory data access in this kernel design without extra address generators is simplified.
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Abstract: Generally, the log-MAP kernel of the turbo decoding consumes large memories in hardware implementation. In this paper, we propose a new log-MAP kernel to reduce memory usage. The comparison result shows our proposed architecture can reduce the memory size to 26% of the classical architecture. We also simplify the memory data access in this kernel design without extra address generators. For the 3GPP standard, a prototyping chip of the turbo decoder is implemented to verify the proposed memory-reduced log-MAP kernel in 3.04/spl times/3.04mm/sup 2/ core area in the UMC 0.18 /spl mu/m CMOS process.
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Citations
Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding
TL;DR: A scalable maximum a posteriori algorithm (MAP) processor designs which can support both single-binary and double-binary CTC decode, and handle arbitrary block sizes for high throughput CTC decoding are proposed.
Memory-reduced MAP decoding for double-binary convolutional Turbo code
Jinjin He,Zhongfeng Wang,Huaping Liu +2 more
- 03 Aug 2010
TL;DR: A memory-reduced VLSI architecture for the decoding of double-binary convolutional Turbo code (DB CTC) using maximum a posteriori probability (MAP) algorithm based on the new formulation of BMs, which leads to 50% reduction of the memory size for BMs.
7
Patent
Method and apparatus for turbo code decoding
Cheng-Hung Lin,An-Yu Wu +1 more
- 30 Apr 2008
TL;DR: In this article, a method and apparatus for turbo code decoding is presented to reduce memory consumption during calculation of state metrics, where the original state metric is converted to a differential metric before being stored into a memory device.
5
Low-power traceback MAP decoding for double-binary convolutional turbo decoder
Cheng-Hung Lin,Chun-Yu Chen,An-Yeu Wu +2 more
- 18 May 2008
TL;DR: The traceback MAP decoding is introduced for double-binary convolutional turbo codes without losing the correction performance, and two proposed traceback structures have a tradeoff between the power and operating frequency.
High-throughput dual-mode single/double binary map processor design for wireless wan
Chun-Yu Chen,Cheng-Hung Lin,An-Yeu Wu +2 more
- 17 Nov 2008
TL;DR: The VLSI implementation of a high-throughput enhanced Max-log-MAP processor that supports both single-binary and double-binary convolutional turbo codes and can be used as hardware accelerators in multistandard platform for wireless WAN with low cost and low energy is presented.
References
Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1
Claude Berrou,A. Glavieux,Punya Thitimajshima +2 more
- 23 May 1993
TL;DR: In this article, a new class of convolutional codes called turbo-codes, whose performances in terms of bit error rate (BER) are close to the Shannon limit, is discussed.
Near Shannon limit error-correcting coding and decoding
Claude Berrou
- 01 Jan 1993
TL;DR: A new class of convolutional codes called turbo-codes, whose performances in terms of bit error rate (BER) are close to the Shannon limit, is discussed.
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An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes
TL;DR: An intuitive shortcut to understanding the maximum a posteriori (MAP) decoder is presented based on an approximation to correspond to a dual-maxima computation combined with forward and backward recursions of Viterbi algorithm computations.
Comparative study of turbo decoding techniques: an overview
Jason Woodard,Lajos Hanzo +1 more
TL;DR: An overview of the novel class of channel codes referred to as turbo codes, which have been shown to be capable of performing close to the Shannon limit, is provided.
VLSI architectures for the MAP algorithm
TL;DR: It is shown that the critical path of the algorithm can be reduced if the add-MAX* operation is reordered into an offset-add-compare-select operation by adjusting the location of registers.
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