Journal Article10.1109/54.7981
A knowledge-based system for selecting test methodologies
X.-A. Zhu,M.A. Breuer +1 more
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TL;DR: A prototype knowledge-based system that helps select test methodologies for a particular type of logic structure is described, which uses a divide-and-conquer (partitioning) strategy and works interactively with a user as an intelligent consultant and assistant.
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Abstract: A prototype knowledge-based system that helps select test methodologies for a particular type of logic structure is described. The system, called TDES, (testable design expert system), is a subsystem of Adam, an advanced design automation system. The system is being used to test programmable logic arrays, but its architecture is applicable to other types of structures such as RAMs, ROMs, and other combinational logic. It uses a divide-and-conquer (partitioning) strategy and works interactively with a user as an intelligent consultant and assistant. >
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Citations
Synthesizing for scan dependence in built-in self-testable designs
L.J. Avra,Edward J. McCluskey +1 more
- 17 Oct 1993
TL;DR: This paper introduces new design and synthesis techniques that reduce the area and performance overhead of built-in self-test (BIST) architectures such as circular BIST and parallel BIST, and shows that introducing certain types of scan dependence in embedded MISRs can result in reduced overhead and improved fault coverage.
49
Generating a family of testable designs using the BILBO methodology
TL;DR: A design system based on the BILBO methodology has been developed that can efficiently explore the testable design space to generate a family of designs ranging from the minimal test time design to the minimal area overhead design.
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Integration of algorithmic VLSI synthesis with testability incorporation
TL;DR: This research differs from other synthesizers by implementing testability as part of the VLSI design solution, and a binary-tree data structure is used throughout the testable design search.
18
Exploring test space with fuzzy decision making
M. Fares,B. Kaminska +1 more
TL;DR: To cope with the increasing number of new designs, the next generation of VLSI design systems will need mechanisms for modeling and managing the design space and the decision-making aspect will dominate both the design process and time.
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An AI constraint network-based approach to bed-of-nails DFT for digital circuit design
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TL;DR: An approach to implementing on-line DFT advice systems which can give designers the kind of feedback that would be provided by test engineers on an AI programming technology called constraint networks is presented.
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References
Design for Testability—A Survey
TL;DR: The different techniques of design for testability are discussed in detail, including techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.
454
A Knowledge-Based System for Designing Testable VLSI Chips
Magdy S. Abadir,Melvin A. Breuer +1 more
TL;DR: This article describes efforts to build a knowledge-based expert system for designing testable VLSI chips and introduces a framework for a methodology incorporating structural, behavioral, qualitative, and quantitative aspects of known DFT techniques.
241
The ADAM Advanced Design Automation System: Overview, Planner and Natural Language Interface
John J. Granacki,David Knapp,Alice C. Parker +2 more
- 01 Jun 1985
TL;DR: ADAM is described, an integrated Advanced Design AutoMation system, with focus on the knowledge-based synthesis subsystem, which includes a number of design activities and utilities, and a unified, multidimensional, hierarchical design representation.
76
A Knowledge Based System for Selecting a Test Methodology for a PLA
Melvin A. Breuer,Xi-an Zhu +1 more
- 01 Jun 1985
TL;DR: A prototype knowledge based system has been developed which simulates a human expert on design of testable PLAs and is able to negotiate with the user so as to lead the user through the design space to find a satisfactory solution.
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Analysis of testable PLA designs
X.-A. Zhu,M.A. Breuer +1 more
TL;DR: A framework is presented for evaluating methods of testing programmable logic arrays (PLAs), and the attributes of 25 test design methodologies are tabulated.
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