Book Chapter10.1007/978-3-540-75444-2_55
A Highly Efficient Parallel Algorithm for H.264 Encoder Based on Macro-Block Region Partition
Shuwei Sun,Dong Wang,Shuming Chen +2 more
- 26 Sep 2007
- pp 577-585
45
TL;DR: Simulation results show that the proposed MBRP parallel algorithm can achieve higher speedups compared to previous approaches, and the encoding quality is the same as JM 10.2.
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Abstract: This paper proposes a highly efficient MBRP parallel algorithm for H.264 encoder, which is based on the analysis of data dependencies in H.264 encoder. In the algorithm, the video frames are partitioned into several MB regions, each of which consists of several adjoining columns of macroblocks (MB), which could be encoded by one processor of a multi-processor system. While starting up the encoding process, the wave-front technique is adopted, and the processors begin encoding process orderly. In the MBRP parallel algorithm, the quantity of data that needs to be exchanged between processors is small, and the loads in different processors are balanced. The algorithm could efficiently encode the video sequence without any influence on the compression ratio. Simulation results show that the proposed MBRP parallel algorithm can achieve higher speedups compared to previous approaches, and the encoding quality is the same as JM 10.2.
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Citations
Evaluation of data-parallel splitting approaches for H.264 decoding
Florian Seitner,Ralf M. Schreier,Michael Bleyer,Margrit Gelautz +3 more
- 24 Nov 2008
TL;DR: This study investigates six methods for accomplishing data-parallel splitting in strongly resource-restricted environments inherent to mobile devices and presents benchmark results using different numbers of processor cores to aid in finding a splitting strategy that is best suited for the targeted hardware-architecture.
A fine-grained parallel implementation of a H.264/AVC encoder on a 167-processor computational platform
Zhibin Xiao,Stephen Le,Bevan M. Baas +2 more
- 01 Nov 2011
TL;DR: The encoder presented is capable of encoding VGA (640 × 480) video at 21 frames per second with 931 mW average power consumption by adjusting each processor to workload-based optimal clock frequencies and dual supply voltages with less than 1dB loss in resolution.
24
A Novel Macro-Block Group Based AVS Coding Scheme for Many-Core Processor
Zhenyu Wang,Luhong Liang,Guolei Yang,Xianguo Zhang,Jun Sun,Debin Zhao,Wen Gao +6 more
- 01 Oct 2011
TL;DR: A Macro-Block Group (MBG) parallel scheme for parallel AVS coding, where each MBG consists of more rows and less columns of macro-blocks than the slice-level scheme, and a vertical partitioning scheme is introduced.
13
Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos
Hong Chinh Doan,Haris Javaid,Sri Parameswaran +2 more
- 01 Dec 2011
TL;DR: The results illustrate that systems with three and seven ASIPs delivered real-time throughput of 30 and 60 fps respectively for “pedestrian”, “rush hour” and “tractor” HD1080p video sequences, and indicate that the multi-ASIP platform can be extended for even higher resolutions such as Ultra High Definition (UHD) due to its flexibility and scalability.
12
A Novel Macro-Block Group Based AVS Coding Scheme for Many-Core Processor
Zhenyu Wang,Luhong Liang,Xianguo Zhang,Jun Sun,Debin Zhao,Wen Gao +5 more
- 15 Dec 2009
TL;DR: A novel Macro-Block Group (MBG) decomposition scheme is presented for parallel AVS coding, and can achieve a reduction of 52% and 41% in quality loss while keeping the same speed-up compared with the slice-level parallelism.
12
References
Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture
Tung-Chien Chen,Yu-Wen Huang,Liang-Gee Chen +2 more
- 23 May 2004
TL;DR: A new macroblock (MB) pipelining scheme for H.264/AVC encoder, which requires computational complexity of 1.8 tera-instructions per second (TIPS), is successfully mapped into hardware with the MB pipeline scheme at 100 MHz.
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Towards efficient multi-level threading of H.264 encoder on Intel hyper-threading architectures
Yen-Kuang Chen,Xinmin Tian,Steven Ge,Milind B. Girkar +3 more
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TL;DR: Two efficient methods for multilevel data partitioning are described that can improve the performance of the multithreaded H.264 encoder using the OpenMP programming model, which allows us to leverage the advanced compiler technologies in the Intel/spl reg/ C++ compiler for Intel hyper-threading architectures.
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Efficient mapping of the H.264 encoding algorithm onto multiprocessor DSPs
Amit Gulati,George Campbell +1 more
TL;DR: This paper addresses issues that arise from the mapping of H.264 onto Multiprocessor DSP chips, and shows flexible methods for mapping the algorithm onto MDSPs which allow scalability over coding tools, resolutions, and computation/bandwidth availability.
19
A thread and data-parallel MPEG-4 video encoder for a system-on-chip multiprocessor
TR Jacobs,Vassilios Chouliaras,Jose L Nunez-Yanez +2 more
- 23 Jul 2005
TL;DR: VLSI macrocells of a vector accelerator implementing a subset of the MPEG-4 vector ISA and a 2-way, parametric, bus-based, cache coherent, SoC multiprocessor are presented.
3
A Highly Efficient Parallel Algorithm for H.264 Video Encoder
Zhuo Zhao,Ping Liang +1 more
- 14 May 2006
TL;DR: A highly efficient parallel algorithm of H.264 encoder that achieves the optimal compression at a frame rate that increases approximately linearly as the number of parallel processing elements and the theoretical encoding time is proposed.