A graph based processor model for retargetable code generation
Johan Van Praet,Dirk Lanneer,Gert Goossens,Werner Geurts,Hugo De Man +4 more
- 11 Mar 1996
- pp 102-107
TL;DR: This paper developed a retargetable and optimising code generator that uses a graph based processor model that captures the connectivity the parallelism and all architectural peculiarities of an embedded processor.
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Abstract: Embedded processors in electronic systems typically are tuned to a few applications. Development of processor specific compilers is prohibitively expensive and as a result such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a retargetable and optimising code generator. It uses a graph based processor model that captures the connectivity, the parallelism and all architectural peculiarities of an embedded processor. In this paper, the processor model is presented and we formally define the code generation task, including code selection, register allocation and scheduling, in terms of this model.
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Citations
A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language
Andreas Hoffmann,Tim Kogel,Achim Nohl,Gunnar Braun,Oliver Schliebusch,Oliver Wahlen,Andreas Wieferink,Heinrich Meyr +7 more
TL;DR: A retargetable framework for ASIP design which is based on machine descriptions in the LISA language is presented which can be generated automatically including high-level language C compiler, assembler, linker, simulator, and debugger frontend.
192
Modern development methods and tools for embedded reconfigurable systems: A survey
TL;DR: This paper reviews the recent methods and tools for the macro- and micro-architecture synthesis, and for the application mapping of reconfigurable systems, and puts much attention to the relevant and currently hot topic of ASIP instruction set processors (ASIP) synthesis.
104
Retargetable generation of code selectors from HDL processor models
Rainer Leupers,Peter Marwedel +1 more
- 17 Mar 1997
TL;DR: This paper presents techniques for automatic generation of code selectors from externally specified processor models from general HDL processor models, which permits study of the HW/SW trade-off between processor architectures and program execution speed.
95
Embedded software in real-time signal processing systems: design technologies
Gert Goossens,J. Van Praet,Dirk Lanneer,Werner Geurts,Augusli Kifli,Clifford Liem,Pierre Paulin +6 more
- 01 Mar 1997
TL;DR: This paper discusses design technology issues for embedded systems using processor cores, with a focus on software compilation tools, and conducts a comprehensive survey of both existing and new software compilation techniques that are considered important in the context of embedded processors.
77
Retargetable compiled simulation of embedded processors using a machine description language
TL;DR: The article discusses the requirements of software development tools on processor models and presents the approach based on the LISA language, and the implementation of a retargetable environment consisting of compiled simulator, debugger, and assembler is presented.
50
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David Landskov,Scott Davidson,Bruce D. Shriver,Patrick W. Mallett +3 more
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TL;DR: A comprehensive terminology for the area is presented, as well as a general model of processor behavior suitable for comparing the algorithms, and the conceptual distinction between data dependency and conflict analysis is emphasized.
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Local Microcode Compaction Techniques
TL;DR: A survey of microcode compaction algorithms can be found in this paper, where a general model of processor behavior suitable for comparing the algorithms is presented. But the authors emphasize the conceptual distinction between data dependency and conflict analysis.
Chess : Retargetable Code Generation for Embedded DSP Processors
Dirk Lanneer,Johan Van Praet,Augusli Kifli,K. Schoofs,Werner Geurts,Filip Thoen,Gert Goossens +6 more
- 01 Jan 2002
TL;DR: This chapter introduces Chess, a retargetable code generation environment for fixedpoint DSP processors that addresses a range of commercial as well as applicationspecific processors, which are increasingly being used for embedded applications in telecommunications, speech and audio processing.
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Optimal code generation for expression trees
Alfred V. Aho,S. C. Johnson +1 more
- 05 May 1975
TL;DR: A dynamic programming algorithm is presented which produces optimal code for any machine in the class; this algorithm runs in time which is linearly proportional to the number of vertices in an expression tree.
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Optimal code generation for embedded memory non-homogeneous register architectures
Guido Araujo,Sharad Malik +1 more
- 13 Sep 1995
TL;DR: This paper proposes and proves the optimality of an O(n) algorithm for the tasks of instruction selection, register allocation and scheduling on a class of architectures defined as the [1,/spl infin/] model.
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