Proceedings Article10.1145/334012.334036
A generic tool set for application specific processor architectures
Frank Engel,Johannes Nührenberg,Gerhard Fettweis +2 more
- 01 May 2000
- pp 126-130
TL;DR: A tool set for fast and easy simulation of processor architectures based on a retargetable simulator core using ANSIC to reduce the development time for designing and validating System-on-a-chip (SoC) applicationsbased on a processor core.
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Abstract: Retargetability allows an easy adoption of a simulator on different processor architectures without a time consuming redesign of all tools. This is evident for an efficient HW/SW codesign. In this paper we describe a tool set for fast and easy simulation of processor architectures based on a retargetable simulator core. This approach helps to reduce the development time for designing and validating System-on-a-chip (SoC) applications based on a processor core. The use of ANSI C avoids an expensive development of a modeling language. Our main focus in this paper is on conceptual decisions are made and on the structure of the tool set.
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Citations
A universal technique for fast and flexible instruction-set architecture simulation
Achim Nohl,Gunnar Braun,Oliver Schliebusch,Rainer Leupers,Heinrich Meyr,Andreas Hoffmann +5 more
- 10 Jun 2002
TL;DR: A novel retargetable simulation technique is presented, which combines the performance of traditional compiled simulators with the flexibility of interpretive simulation and is demonstrated by means of state-of-the-art real-world architectures.
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Mehrdad Reshadi,Prabhat Mishra,Nikil Dutt +2 more
- 02 Jun 2003
TL;DR: This paper presents a novel technique for generation of fast instruction-set simulators that combines the benefit of both compiled and interpretive simulation and uses a novel instruction abstraction technique to generate aggressively optimized decoded instructions that further improves simulation performance.
An efficient retargetable framework for instruction-set simulation
Mehrdad Reshadi,Nikhil Bansal,Prabhat Mishra,Nikil Dutt +3 more
- 01 Oct 2003
TL;DR: In this paper, a generic instruction model and a generic decode algorithm are developed to facilitate easy and efficient retargetability of the ISA-simulator for a wide range of processor architectures such as RISC, CISC, VLIW and variable length instruction set processors.
A universal technique for fast and flexible instruction-set architecture simulation
TL;DR: A novel retargetable simulation technique is presented, which combines the performance of traditional compiled simulators with the flexibility of interpretive simulation and is demonstrated by means of state-of-the-art real-world architectures.
48
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation
TL;DR: This article improves the interpretive simulation performance by applying compiled simulation at the instruction level using a novel template-customization technique to generate optimized decoded instructions during compile time and reduces the compile-time overhead by combining the benefits of both static and dynamic-compiled simulation.
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