Journal Article10.1109/JSSC.2014.2319254
A Filtering Delta Sigma ADC for LTE and Beyond
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TL;DR: A filtering ADC for the LTE communication standard, where a second-order Delta-Sigma modulator (DSM) is incorporated into the third-order Chebyshev channel-select filter of the radio receiver, and a design method for the filtering ADC accounting for unavoidable DSM-DAC delays is developed and experimentally demonstrated.
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Abstract: This paper presents a filtering ADC for the LTE communication standard, where a second-order Delta-Sigma modulator (DSM) is incorporated into the third-order Chebyshev channel-select filter (CSF) of the radio receiver. The CSF introduces an additional third-order suppression of both thermal and quantization DSM noise, while the CSF transfer function is maintained. A design method for the filtering ADC accounting for unavoidable DSM-DAC delays is developed and experimentally demonstrated. The 65 nm CMOS prototype is clocked at 576/288 MHz with an 18.5/9.0 MHz LTE bandwidth, has an in-band gain of 26 dB, an SNDR of 56.4/58.1 dB, an input-referred noise of 5 nV/ √{Hz}, and an out-of-band (half-duplex) IIP3 of 20/12 dBV rms , with a power consumption of 7.9/5.4 mW and an overall state-of-the art performance.
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Citations
Continuous-time delta-sigma modulator with maximally flat signal transfer function using minimum number of DACs
Changsok Han,Arun Javvaji,Nima Maghari +2 more
- 01 Aug 2017
TL;DR: A 4th order CTDSM with a chain of feedback structure is used to achieve maximally flat STF, while the required number of digital-to-analog converters in the traditional CIFB structure is minimized.
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Blocker and Clock-Jitter Performance in CT ΣΔ ADCs for Consumer Radio Receivers
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Filtering ADCs for wireless receivers: A survey
Qiwei Wang,Antonio Liscidini,Anthony Chan Carusone +2 more
- 01 Aug 2017
TL;DR: This paper reviews and analyzes two design methodologies for analog filtering ADCs, where the filter response is defined by analog circuits and a digital filtering ADC architecture is discussed that takes advantage of the programmability of digital circuits.
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Design of Continuous-Time Delta-Sigma Modulators
Qiyuan Liu,Alexander Edward,Carlos Briseno-Vidrios,Jose Silva-Martinez +3 more
- 01 Jan 2018
TL;DR: This chapter presents the analysis and design of continuous-time ΔΣ modulators (CTΔΣMs) with a focus on single-loop topology, and the effects of non-idealities such as the excess loop delay (ELD) and the feedback DAC’s clock jitter on the performance of CTΔ ΣMs are discussed.
1
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A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB
Gerhard Mitteregger,Christian Ebner,Stephan Mechnig,T. Blon,Christophe Holuigue,Ernesto Romani +5 more
TL;DR: A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS and the degradation of modulator stability due to excess loop delay is avoided with a new architecture.
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A 4th-order active-G/sub m/-RC reconfigurable (UMTS/WLAN) filter
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