Journal Article10.1109/JSSC.2014.2319254
A Filtering Delta Sigma ADC for LTE and Beyond
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TL;DR: A filtering ADC for the LTE communication standard, where a second-order Delta-Sigma modulator (DSM) is incorporated into the third-order Chebyshev channel-select filter of the radio receiver, and a design method for the filtering ADC accounting for unavoidable DSM-DAC delays is developed and experimentally demonstrated.
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Abstract: This paper presents a filtering ADC for the LTE communication standard, where a second-order Delta-Sigma modulator (DSM) is incorporated into the third-order Chebyshev channel-select filter (CSF) of the radio receiver. The CSF introduces an additional third-order suppression of both thermal and quantization DSM noise, while the CSF transfer function is maintained. A design method for the filtering ADC accounting for unavoidable DSM-DAC delays is developed and experimentally demonstrated. The 65 nm CMOS prototype is clocked at 576/288 MHz with an 18.5/9.0 MHz LTE bandwidth, has an in-band gain of 26 dB, an SNDR of 56.4/58.1 dB, an input-referred noise of 5 nV/ √{Hz}, and an out-of-band (half-duplex) IIP3 of 20/12 dBV rms , with a power consumption of 7.9/5.4 mW and an overall state-of-the art performance.
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Citations
A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers
TL;DR: This paper presents a long-term evolution (LTE) receiver (RX) front end with a digital filtering analog to digital converter (ADC) in the baseband to perform multi-band blocker cancellation.
8
STF engineering in CT sigma-delta modulators using www.sigma-delta.de
Johannes Wagner,Rudolf Ritter,Maurits Ortmanns +2 more
- 27 Jun 2016
TL;DR: The web-based design tool for continuous-time ΣΔ modulators relies on a heuristic search based on a genetic algorithm that is able to determine a STF complying to given constraints while maximizing the signal-to-noise ratio of the chosen modulator architecture at the same time.
8
A 0.6-3.0 GHz 65 nm CMOS Radio Receiver with DS-based A/D-Converting Channel-Select Filters
Anders Nejdel,Xiaodong Liu,Mattias Palm,Lars Sundström,Markus Tormanen,Henrik Sjöland,Pietro Andreani +6 more
- 02 Nov 2015
TL;DR: A wideband quadrature radio receiver employing ΔΣ-based A/D-converting channel-select filters (AD-CSFs) which incorporate the functionalities of both channel selection and data conversion in a single power-optimized block is presented.
8
Continuous-Time Delta-Sigma ADCs With Improved Interferer Rejection
Rudolf Ritter,Maurits Ortmanns +1 more
TL;DR: This paper intends to review the motivation, to give a tutorial of the state of the art, as well as to introduce a deeper analysis for DSM with interferer robustness, and to analyzes state-of-the-art techniques of modulators with improved interferer rejection.
8
•Dissertation
Continuous-Time Delta-Sigma Modulators for Wireless Communication
Mattias Andersson
- 01 Jan 2014
TL;DR: This dissertation contains an introduction to the field and five papers that focus on the continuous-time (CT) Delta-Sigma modulator (DSM) as ADC, where the DSM is merged into the channel select filter to suppress the noise from the DSM.
References
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A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB
Gerhard Mitteregger,Christian Ebner,Stephan Mechnig,T. Blon,Christophe Holuigue,Ernesto Romani +5 more
TL;DR: A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS and the degradation of modulator stability due to excess loop delay is avoided with a new architecture.
341
A 4th-order active-G/sub m/-RC reconfigurable (UMTS/WLAN) filter
TL;DR: A fourth-order low-pass continuous-time filter for a UMTS/WLAN receiver of a reconfigurable terminal is presented and the full chip has been designed using an automatic design tool, which is validated by the agreement between the experimental results and the expected performance.
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