Open AccessJournal Article10.1016/J.MICROREL.2018.07.092

A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

- 01 Sep 2018

- Iss: 88, pp 355-359

TL;DR: A defect-oriented test that uses On-Chip Current Sensors to detect weak resistive defects by monitoring the current consumption of FinFET SRAM cells is presented, and simulation results show that the approach is even able to detectWeak resistives that do not sensitize faults at the functional level, thus able to increase the reliability of devices.

About: This article is published in Microelectronics Reliability. The article was published on 01 Sep 2018. and is currently open access. The article focuses on the topics: Reliability (semiconductor) & Resistive touchscreen.

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1. What contributions have the authors mentioned in the paper "Delft university of technology a defect-oriented test approach using on-chip current sensors for resistive defects in finfet srams" ?

This paper presents a defect-oriented test that uses On-Chip Current Sensors ( OCCS ) to detect weak resistive defects by monitoring the current consumption of FinFET SRAM cells.

2. What are the future works mentioned in the paper "Delft university of technology a defect-oriented test approach using on-chip current sensors for resistive defects in finfet srams" ?

In the future, the authors would like to analyse the impact of inter-cell defects as well.

Fig. 4. Simulation of defect DFB2 (a) input of OCCSs (b) output of OCCSs

Fig. 5. Area overhead for different column sizes.

Fig. 3. Simulation of defect DFO2 (a) input of OCCSs (b) output of OCCSs

Fig. 1. Set of Resistive defects injected in memory cells: (a) Resistive-Open and (b) Resistive-Bridge defects.

Fig. 2. Architecture of the proposed hardware-based approach.

Citations

•Journal Article

Introduction to Nanotechnology

健一伊賀, +1 more

- 01 Nov 2002

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•Journal Article•10.1109/TVLSI.2021.3071940

Hard-to-Detect Fault Analysis in FinFET SRAMs

Guilherme Cardoso Medeiros, +5 more

- 20 Apr 2021

- IEEE Transactions on Very Large Scale In...

TL;DR: Improved detection of HTD faults in FinFET SRAMs could be achieved by using parametric test solutions, proposing solutions that cover yet-untargetedHTD faults, combining multiple test approaches into a single solution, and further exploring stress conditions.

...read moreread less

•Proceedings Article•10.23919/DATE48585.2020.9116278

A DFT scheme to improve coverage of hard-to-detect faults in FinFET SRAMs

Guilherme Cardoso Medeiros, +6 more

- 09 Mar 2020

TL;DR: This paper proposes a new design-for-testability (DFT) scheme for FinFET SRAMs to detect such faults by creating a mismatch in the sense amplifier (SA) that will incorrectly bias the SA and cause incorrect read outputs.

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Journal Article•10.1109/TDMR.2021.3104764

CD-DFT: A Current-Difference Design-for-Testability to Detect Short Defects of STT-MRAM Under Process Variations

Shiva Taghipour, +4 more

- 16 Aug 2021

- IEEE Transactions on Device and Material...

TL;DR: In this paper, a low area overhead design-for-testability (DFT) circuit is proposed to detect resistive short defects in STT-MRAM arrays, which is based on monitoring the current mismatch flowing into and out of the cell caused by a weak or strong short defect.

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Proceedings Article•10.1109/ETS50041.2021.9465441

Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs

G. Cardoso Medeiros, +5 more

- 24 May 2021

TL;DR: In this paper, the authors proposed a new Design-For-Testability (DFT) scheme for FinFET SRAMs to detect RRF using SCs that improve the detection rate of RRFs.

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References

Journal Article•10.1109/JPROC.2002.808156

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

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A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

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Most frequently asked questions

1. What contributions have the authors mentioned in the paper "Delft university of technology a defect-oriented test approach using on-chip current sensors for resistive defects in finfet srams" ?

2. What are the future works mentioned in the paper "Delft university of technology a defect-oriented test approach using on-chip current sensors for resistive defects in finfet srams" ?

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Citations

Introduction to Nanotechnology

Hard-to-Detect Fault Analysis in FinFET SRAMs

A DFT scheme to improve coverage of hard-to-detect faults in FinFET SRAMs

CD-DFT: A Current-Difference Design-for-Testability to Detect Short Defects of STT-MRAM Under Process Variations

Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs

References

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

FinFETs and Other Multi-Gate Transistors

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

Introduction to Nanotechnology

Technology and design challenges for low power and high performance

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