A compositional minimization approach for large asynchronous design verification

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1. What are the contributions in "A compositional minimization approach for large asynchronous design verification" ?

2. What have the authors stated for future works in "A compositional minimization approach for large asynchronous design verification" ?

3. How do the authors verify a design using the compositional minimization method?

4. What is the definition of the abstraction relation between two SGs?

Accepted Answer

This paper presents a compositional minimization approach with efficient state space reductions for verifying non-trivial asynchronous designs.

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In the future, it is necessary to experiment on more diverse examples including communication protocols and multithreaded programs to fully demonstrate its potential.

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To verify a design using the compositional minimization method in this paper, all components in the design need to be converted to SGs first.

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In the actual implementation, when composing two SGs, a reachability analysis algorithm is performed from the initial composite state following the definition for transition relation R, and therefore, the resulting composite SG contains only the reachable states.

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This paper presents a compositional minimization approach with a number of state graph reductions to lower the verification complexity while not introducing extra paths that might cause false failures nor reducing any essential behaviors.

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If the failure state is involved in nondeterminism, redundant state transitions are identified based on the following understanding: if an action in a state may or may not cause a failure nondeterministically, it is always regarded as causingIXa failure.

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for each visible transition in states si+1, sj+1, and sk+1, a new transition on the same action is created for states si, sj , and sk, respectively.

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Function oer(G, s1, s2), as shown in Algorithm 2, searches forwards bypassing each invisible state transition from s2 in the depth-first manner until a visible transition or the failure state π is encountered.

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The reductions remove certain state transitions and states from a state graph in such a way that the observable behavior on the interface remains the same.

Accepted Answer

The SG produced by reduce(G) in Algorithm 1 inherits every element of G except the updated R and S. The algorithm reduce(G) checks each invisible state transition (s1, a1, s2) in G, and calls another function oer(G, s1, s2) if the start state s1 of that invisible state transition has at least one incoming state transition that is visible.

Accepted Answer

the redundancy removal techniques presented in this paper can help to remove a lot of these redundancy introduced by the observably equivalent reduction to significantly simply the complexity of SGs.

Accepted Answer

The reduced state graphs are observably equivalent to the original ones, which implies that any properties hold or fail in the reduced SGs if, and only if, they hold or fail in the original ones.

A compositional minimization approach for large asynchronous design verification

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Most frequently asked questions

1. What are the contributions in "A compositional minimization approach for large asynchronous design verification" ?

2. What have the authors stated for future works in "A compositional minimization approach for large asynchronous design verification" ?

3. How do the authors verify a design using the compositional minimization method?

4. What is the definition of the abstraction relation between two SGs?

5. What is the purpose of this paper?

6. What is the definition of failure equivalent transitions?

7. What is the process of removing invisible transitions from G?

8. What is the oer function in the Algorithm 2?

9. What is the purpose of the reduction method?

10. What is the function oer(G) used to check the invisible state transitions?

11. What is the effect of the redundancy removal techniques presented in this paper?

12. What is the purpose of the reduced state graphs?

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Citations

Verification methodologies for fault-tolerant Network-on-Chip systems

Compositional Model Checking of Concurrent Systems

Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits

You assume, we guarantee : Methodology and case studies

References

A lightweight approach for loop summarization

An improvement in formal verification.

Compositionality: The Significant Difference

Automated Assume-Guarantee Reasoning by Abstraction Refinement

Compositional reasoning in model checking

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