A component selection algorithm for high-performance pipelines
Smita Bakshi,Daniel D. Gajski +1 more
- 23 Sep 1994
- pp 400-405
TL;DR: A cost-optimized algorithm for selecting components and pipelining a data flow graph, given a multiple-implementation library, and throughput and latency constraints is presented.
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Abstract: Author(s): Bakshi, Smita; Gajski, Daniel D. | Abstract: The use of a realistic component library with multiple implementations of operators, results in cost efficient designs; slow components can then be used on non-critical paths and the more expensive components on only the critical paths. This report presents a cost-optimized algorithm for selecting components and pipelining a data flow graph, given a multiple-implementation library, and throughput and latency constraints. Results on several DSP examples indicate the importance of component selection as a parameter in design space exploration.
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Citations
SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design
TL;DR: The SpecSyn system-level design environment is presented, which supports the new specify-explore-refine (SER) design paradigm, and the new paradigm and environment are expected to lead to a more than ten times reduction in design time.
Partitioning and pipelining for performance-constrained hardware/software systems
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TL;DR: The ability to incorporate partitioning with pipelining at several levels of granularity enables the author to attain high throughput designs, and also distinguishes this paper from previously proposed hardware/software partitioning algorithms.
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A memory selection algorithm for high-performance pipelines
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- 01 Dec 1995
TL;DR: This paper presents an algorithm to select a memory organization, in addition to selecting a pipeline and other datapath components, given performance constraints, and conducts experiments to give a quantitative measure of the impact of memory selection on DSP design.
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A placement driven methodology for high-level synthesis of sub-micron ASIC's
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TL;DR: This paper proposes a novel methodology for automated data-path synthesis of deep submicron Application Specific Integrated Circuits by formulate interconnect area/delay optimizations as high-level synthesis transformations and use them during the synthesis to minimize impact of wiring on circuit characteristics.
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Enabling High-Level Synthesis Resource Sharing Design Space Exploration in FPGAs Through Automatic Internal Bitwidth Adjustments
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References
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N. Park,Alice C. Parker +1 more
TL;DR: Sehwa can find the minimum-cost design, the highest performance design, and other designs between these two in the design space and executes within minutes, for problems of practical size, on a VAX 11/750.
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Scheduling and hardware sharing in pipelined data paths
Ki Soo Hwang,A.E. Casavant,C.-T. Chang,M.A. d'Abreu +3 more
- 05 Nov 1989
TL;DR: A scheduling and hardware sharing algorithm that tries to distribute operations equally among partitions to maximize hardware sharing and has been used successfully for synthesizing a pipelined data path from a graphics processing description that contains about 1000 components.
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Rajiv Jain,Alice C. Parker,Nohbyung Park +2 more
- 01 Jun 1988
TL;DR: A model for estimating area-time tradeoffs for pipelined designs is used to formulate the problem, and an overview of the solution technique is given; Complexities introduced by nonoptimal designs and user constraints are addressed.
63
An algorithm for component selection in performance optimized scheduling
L. Ramachandran,D.D. Gajski +1 more
- 11 Nov 1991
TL;DR: A novel algorithm is described that combines the hardware scheduling and component selection phases for high level synthesis, by being able to simultaneously select components from a given library, which enlarges the design space, resulting in better optimized designs.
54
PLS: a scheduler for pipeline synthesis
TL;DR: It is shown that the delay time for executing an iteration of a loop has a strong relationship to the cost of the registers and the controller, so by minimizing the delay, there is more silicon area to allocate to additional resources, which increases throughput.
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