Proceedings Article10.1109/TENCON.2007.4429017
A combined multiplication/division algorithm for efficient design of ECC over GF(2 m )
Wen-Ching Lin,Jun-Hong Chen,Ming-Der Shieh,Chien-Ming Wu +3 more
- 01 Oct 2007
- pp 1-4
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TL;DR: This paper shows that a field multiplication over GF(2m) can be implemented by the extended Stein algorithm, one of the algorithms used to realize division, and achieves area advantages in comparison with other low-cost designs.
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Abstract: Using the concept of reciprocal polynomial, this paper shows that a field multiplication over GF(2m) can be implemented by the extended Stein algorithm, one of the algorithms used to realize division. With a fundamental change at the algorithmic level, the field multiplication can be efficiently embedded into a divider so that the multiplier can be eliminated with very little hardware overhead for operand selection. When applied to elliptic curve cryptography (ECC) using affine coordinates, about 13.8% reduction on the area requirement can be achieved with almost no performance degradation compared with the one implemented with two distinct components. Experimental results show that the combined multiplication and division circuit achieves area advantages in comparison with other low-cost designs. The area-efficient design of ECC system also exhibits obvious improvement in area-time (AT) complexity.
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Citations
New systolic array architecture for finite field division
TL;DR: The proposed systolic array architecture to perform division operations over GF(2m) based on the modified Stein's algorithm has the advantage of reducing the number of flip-flops required to store the intermediate variables of the algorithm and hence reduces the total gate counts to a large extent compared to the other related designs.
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Unified systolic array architecture for finite field multiplication and inversion
TL;DR: A new unified systolic array architecture to perform multiplication and inversion operations in GF(2m) based on the bit serial multiplication algorithm and the previously modified extended Euclidean algorithm is proposed.
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Scalable digit-serial processor array architecture for finite field division
Atef Ibrahim,Atef Ibrahim +1 more
TL;DR: The presented processor array structure can achieve the time performance requirement of a certain application with minimum hardware resources and has a lower area-time product than previously reported designs.
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A digit-serial architecture for inversion and multiplication in GF(2 M )
Junfeng Fan,Ingrid Verbauwhede +1 more
- 17 Nov 2008
TL;DR: This paper describes a unified digit-serial inverter/multiplier in GF(2m) based on a modified Extended Euclidean Algorithm (EEA), while the multiplication is based a LSB-first multiplication algorithm.
11
A Combined Circuit for Multiplication and Inversion in
Katsuki Kobayashi,Naofumi Takagi +1 more
- 01 Jan 2008
TL;DR: A combined circuit for multiplication and inversion in GF(2m) is proposed by combining the most significant bit first multiplication algorithm and the modified extended Euclid's algorithm by focusing on the similarities between them.
8
References
Systolic array implementation of multipliers for finite fields GF(2/sup m/)
Chin-Liang Wang,Jung-Lung Lin +1 more
TL;DR: Two architectures for fast multiplication in finite fields GF(2/sup m/) with the standard basis representation possess features of regularity, modularity, concurrency, and unidirectional data flow and are well suited to VLSI implementation with fault-tolerant design.
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On computing multiplicative inverses in GF(2/sup m/)
TL;DR: The design of a modular standard basis inversion for Galois fields GF(2/sup m/) based on Euclid's algorithm for computing the greatest common divisor of two polynomials is presented, resulting in an AT-complexity of O(m/sup 2/).
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Customizable elliptic curve cryptosystems
TL;DR: The resulting hardware implementations are among the fastest reported: for a key size of 270 bits, a point multiplication in a Xilinx XC2V6000 FPGA at 35 MHz can run over 1000 times faster than a software implementation on a Xeon computer at 2.6 GHz.
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A microcoded elliptic curve processor using FPGA technology
Philip H. W. Leong,I.K.H. Leung +1 more
TL;DR: The implementation of a microcoded elliptic curve processor using field-programmable gate array technology is described, enabling curve operations to be incorporated into the processor and hence reducing the chip's I/O requirements.
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