Open AccessProceedings Article
A 53-GOPS programmable vision processor for processing, coding-decoding and synthesizing of images
Ulrich Ramacher,W. Raab,N. Bruls,U. Hachmann,C. Sauer,Alexander Schackow,J. Gliese,Jens Harnisch,M. Richter,E. Sicheneder,R. Schuffny,U. Schulze,H. Feldkamper,C. Lutkemeyer,H. Susse,S. Altmann +15 more
- 01 Jan 2001
- pp 133-136
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TL;DR: It is the set of 205 application-specific instructions and its computing and memory architecture that make the vision processor a generic one.
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Abstract: whereas virtual round-table conferencing needs at the sender’s side to find a person’s head, cut it from the background, code it and at the receiver’s side to decode and insert it at the round-table by means of geometric transformations (figure below shows virtual round table) Hence, a vision processor has to support image processing, coding/decoding and 3D graphics Accordingly, a representative body of algorithms from these 3 vision fields was analysed with respect to computational power, elementary instructions and data types needed It was found that scalar, vector and matrix constitute the main data types, and a set of 205 visionbased instructions for vector and matrix types was defined Architectural studies led to a parallel array of 16 processing elements (PE) executing the vision instructions on vector and matrix data, as well as to special cache architectures adapted to the new data types For decoding of instructions, a set of controllers had to be introduced that would deliver control bits to the amount of what full-fledged general-purpose processors use to generate, but at a decade lower power level Finally, starting off from the OAK DSP and its Ccompiler, a programming model extending C by some vision based semantics, but keeping the C syntax was thought to be adequate for the user It is the set of 205 application-specific instructions and its computing and memory architecture that make the vision processor a generic one (see [1] for recent alternatives) In the following, only the functional highlights are reported
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Citations
An FPGA implementation of a flexible, parallel image processing architecture suitable for embedded vision systems
S. McBader,Peter Lee +1 more
- 22 Apr 2003
TL;DR: The design of a programmable parallel architecture that is to be used for signal pre-processing in intelligent embedded vision systems and has been implemented and tested using a Celoxica RC1000 prototyping platform with a Xilinx XCY2000E FPGA.
52
A 100-GOPS programmable processor for vehicle vision systems
TL;DR: New generations of automobiles will include driver assistance systems requiring powerful, low-cost processors to handle video/camera applications and to enable fast, convenient application development, bringing substantial increases in system speed and functionality.
39
A programming model for an embedded media processing architecture
Dan Zhang,Zeng-Zhi Li,Hong Song,Long Liu +3 more
- 18 Jul 2005
TL;DR: Experimental results show that SPUR provides programmer a novel, expressive and efficient programming way, and obviously improves readability, robustness, development efficiency and object-code quality of media applications.
26
Insect-vision inspired collision warning vision processor for automobiles
TL;DR: A dedicated sensory-processing architecture for collision warning which is inspired by insect vision is described which is integrated into model cars as well as into a commercial car and tested to deliver collision warnings in real traffic scenarios.
A programmable image signal processing architecture for embedded vision systems
S. McBader,Peter Lee +1 more
- 07 Nov 2002
TL;DR: This paper presents a programmable multiprocessor architecture suitable for image preprocessing in embedded vision systems, made up of sixteen 16-bit input/32-bit output parallel processing elements, connected to an intelligent DMA channel and frame buffers.
8
References
A 4 GOPS 3 way-VLIW image recognition processor based on a configurable media-processor
Yoshihisa Kondo,Takashi Miyamori,T. Kitazawa,S. Inoue,H. Takano,I. Katayama,K. Yahagi,A. Ooue,T. Tamai,Kazuyoshi Kohno,Y. Asao,H. Fujimura,H. Uetani,Y. Inoue,S. Asano,Yukimasa Miyamoto,A. Yamaga,Y. Masubuchi,T. Furuyama +18 more
- 05 Feb 2001
TL;DR: A 4 GOPS 3-way VLIW image-recognition processor for an automobile system is based on a configurable media-processor which enables design-time configuration to optimize for a specific application.
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•Journal Article
A 4GOPS 3 Way-VLIW Image Recognition Processor Based on a Configurable Media Processor
TL;DR: A 4 GOPS 3-way VLIW image recognition processor for an automobile system based on a configurable media-processor which enables design-time configuration to optimize for a specific application is described in this paper.
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Single-chip video camera with multiple integrated functions
Ulrich Ramacher,Ivo Koren,H. Geib,C. Heer,T. Kodytek,J. Werner,J. Dohndorf,J.-U. Schlussler,J. Poidevin,S. Kirmser +9 more
- 15 Feb 1999
TL;DR: This b/w CMOS camera with active pixel cells offers a maximum resolution of 720 pixels per line at 576 lines and a window can be programmed for areas of the image to be tracked for focused exposure measurement.