Proceedings Article10.1109/ISCAS.2012.6271498
A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter
Sally Safwat,Amr M. Lotfy,Maged Ghoneima,Yehea Ismail +3 more
- 20 May 2012
- pp 1371-1374
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TL;DR: The proposed design results in a significant reduction in the area and power compared to other time-to-digital converter (TDC) based ADPLL architectures from eliminating the need for complex, power, and area consuming TDC block, and arrayed DCO.
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Abstract: This paper presents the design and the implementation of a low power bang-bang all digital phase locked loop (BBADPLL). The design of the proposed architecture is based on the programmable coefficients of the digital loop filter (DLF) that manages the tradeoffs between stability and jitter of a closed loop. A proposed simple digital controlled oscillator (DCO) based on three stages ring oscillator provides a wide frequency range, and proven to be of lower area and power compared to arrayed DCO. The proposed design results in a significant reduction in the area and power compared to other time-to-digital converter (TDC) based ADPLL architectures. This reduction results from eliminating the need for complex, power, and area consuming TDC block, and arrayed DCO. A counter-based frequency acquisition loop using a binary search algorithm reduced the lock-in time significantly compared to similar work. The proposed BBADPLL architecture was implemented on TSMC CMOS 65nm technology with a frequency range 5–10GHz and a frequency resolution equals to 500MHz. The lock-in time is 2.4µs. The peak-to-peak period jitter and the RMS jitter at 10GHz are 1.49ps and 0.19ps, respectively. The total power consumed at 10GHz is only 2.7mWatt and the total area of the proposed ADPLL is 4372µm2, which is very small compared to other published architectures.
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Citations
Design and Analysis of Phase Locked Loop and Performance Parameters
TL;DR: In this PLL circuit, which is simulated in CMOS 0.18μm technology, the digital phase locked loop achieves locking within about 100 reference clock cycles, and successfully achieved 1.55GHz frequency.
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Analysis of a class of decimated clock/data recovery architectures for serial links
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Discrete Loop Filter for Time-Synchronization: An Approach from Design to Real Implementation with RTL-SDR Systems
Richard Riddell
- 01 Jan 2023
TL;DR: In this article , the authors highlight Discrete Loop Filter design features for time synchronization Phase Locked Loops (PLL) based on coefficient calculation and adapt the digital filter Type 2 to the PLL scheme to improve the Time to Achieve Lock and reduce the steady state error.
A Low Jitter – Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer Cmos Technology
Dr. Nilesh D. Patel,Dr. Amisha P. Naik,Dr. Priyesh P. Gandhi +2 more
TL;DR: A low-jitter, low-phase noise wideband digital PLL is designed in 180nm CMOS technology, achieving 121.14 dBc/Hz phase noise and 110 fs rms jitter at 7.5-GHz, with 13.99 mW power consumption and robustness against process variations.
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Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs
TL;DR: An approach to the determination of Kbpd is developed which takes into consideration also the effect of the BBPLL dynamics on the effective jitter seen by the BPD, and is based on modeling the dynamics of aBBPLL as a Markov chain.
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A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS
Werner Grollitsch,Roberto Nonis,Nicola Da Dalt +2 more
- 18 Mar 2010
TL;DR: State of the art digital PLLs can be divided in two categories, depending on the implementation of the digital phase detector, which allow fractional-N synthesis, but require high architecture complexity, need calibration routines for period normalization, and introduce analog limitations that a digital P LL should be intended to eliminate.
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