Proceedings Article10.1109/IMC-5G47857.2019.9160355
A 21 to 31 GHz Multi-Stage Stacked SOI Power Amplifier with 33% PAE and 18 dBm Output Power
Tiantong Ren,Brian Floyd +1 more
- 01 Aug 2019
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TL;DR: In this article, a two-stage K/Ka-band power amplifier (PA) implemented on GlobalFoundries 4SRFSOI CMOS technology for 5G millimeterwave phased arrays is presented.
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Abstract: This paper presents a compact two-stage K/Ka-band power amplifier (PA) implemented i n GlobalFoundries 4SRFSOI CMOS technology for fifth-generation (5G) millimeterwave phased arrays. The PA features a linear pre-driver stage with 1.6 V supply and a three-stack FET output stage with 3.6 V supply. Measurement results show that at 26 GHz, the PA achieves a peak gain of 16.6 dB and a saturated output power (P sat ) of 18.3 dBm with maximum power-added efficiency (PAE) of 32.8%. The 1-dB compression point (P 1dB ) is 16.2 dBm with PAE of 29.7%. The PA operates across 21 to 31 GHz with P sat above 17.3 dBm and gain above 13.6 dB.
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Citations
A 20-33 GHz Direct-Conversion Transmitter in 45-nm SOI CMOS
Tiantong Ren,Sandeep Hari,Brian Floyd +2 more
- 16 Nov 2020
TL;DR: In this article, a 20-33 GHz direct-conversion transmitter implemented in 45-nm RFSOI CMOS technology is presented, which uses a divider-based quadrature clock generation circuit, two current-combined double-balanced mixers, and a balanced power amplifier employing stacked FETs.
References
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TL;DR: In this paper, stacked field effect transistor (FET) CMOS millimeter-wave power amplfiers (PAs) are studied with a focus on design of appropriate complex impedances between the transistors.
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Millimeter-Wave Wafer-Scale Silicon BiCMOS Power Amplifiers Using Free-Space Power Combining
TL;DR: In this paper, the first millimeter-wave wafer-scale power-amplifier array implemented in a 0.13-μm m BiCMOS technology was demonstrated with an equivalent isotropic radiated power of 33-35 dBm.
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A Review of 5G Power Amplifier Design at cm-Wave and mm-Wave Frequencies
TL;DR: This review will focus on the available options of device technologies, novel circuit and system architectures, and efficiency enhancement techniques at power back-off for 5G PA design.
A 28-GHz SiGe BiCMOS PA With 32% Efficiency and 23-dBm Output Power
TL;DR: This paper presents a two-stage, four-way combined power amplifier operating in the 27–31-GHz frequency range in 180-nm SiGe BiCMOS technology and presents a co-optimization technique for the transformer and the adjoining matching components to minimize the power loss of the full output network.
41
A 28-GHz Harmonic-Tuned Power Amplifier in 130-nm SiGe BiCMOS
Anirban Sarkar,Brian Floyd +1 more
TL;DR: In this article, the authors present a parasitic-aware design technique for the output network realized as a bandpass filter cascaded with or surrounded by a low-pass matching network.
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